Semiconductor integrated circuit device including memory cells h

Details Semiconductor integrated circuit device including memory cells h Semiconductor integrated circuit device including memory cells h

1992-04-29

1994-09-20

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, H01L 2978

Patent

active

053492188

ABSTRACT:
A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line. The information storage capacitor includes a second insulating film formed on the wall of one trench formed on the main surface of the substrate, an electrode layer formed on the second insulating film and serving as a first electrode of the capacitor, a dielectric film formed on the electrode layer and a conducting material provided to fill a space defined by the dielectric film in the trench and serving as a second electrode of the capacitor. The second doped region of the transistor terminates at the wall of the trench. A conducting layer is provided to extend both on the second doped region and the conducting material in the cell to electrically interconnect them for the series connection.

REFERENCES:
JEE Journal of Electronic Engineering, vol. 26, No. 268, Apr. 1989, pp. 68-70, "Toshiba Presents 45ns 16M-Bit DRAM with Triple-Well Structure".
International Electron Devices Meeting 1988, Technical Digest, Dec. 1988, W. Wakamiya et al.: "Fully Planarized 0.5 .mu.m Technologies for 16M DRAM".

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