Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1993-11-10
1995-10-10
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
326 18, 326108, H03K 190175, H03K 1908
Patent
active
054574129
ABSTRACT:
A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.
Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.
Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.
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Hiramoto Toshiro
Odaka Masanori
Ohayashi Masayuki
Saito Kayoko
Tamba Nobuo
Hitachi , Ltd.
Santamauro Jon
Westin Edward P.
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