Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-20
2003-08-05
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000
Reexamination Certificate
active
06603162
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and to a process for manufacturing the same and, in particular, the invention relates to a process which can effectively be applied to a semiconductor integrated circuit device comprising a step for flattening a surface using CMP (Chemical Mechanical Polishing).
In semiconductor integrated circuit devices, such as a DRAM (Dynamic Random Access Memory), demand has been increasing in recent years for finer detail and a higher degree of integration. Due to the demand for greater detail in semiconductor integrated circuit devices, laminated structures in multilayer interconnections are unavoidable, but if a multilayer structure is used, imperfections are formed on the surface of the upper layer reflecting the imperfections in the substrate. If photolithography is performed when imperfections are present on the surface, sufficient tolerance of focal depth cannot be obtained in the exposure step, and this leads to poor resolution. Therefore, the surface is flattened using CMP in order to improve the photolithography of components formed on the surface.
The CMP technique is used also to form isolation regions. In the LOCOS (Local Oxidation of Silicon) technique, which was frequently used in the past, it is difficult to achieve more than a certain amount of detail due to the presence of a bird's beak. Thus, a shallow groove is formed on a main surface of the semiconductor substrate; this groove is filled with a silicon oxide film; and the silicon oxide in the regions outside the groove are removed by CMP to form a shallow groove isolation. With a shallow groove isolation, the periphery of the isolation region is sharply defined, so the periphery can also be used effectively as an element part, so that it is easier to achieve finer detail.
However, when the CMP technique is used for polishing, it is impossible to completely remove surface imperfections. When there are imperfections on the polishing surface, a history of imperfections remains on the polishing surface to some extent. Further, if parts which are easily polished and parts which are difficult to polish are both present on the polishing surface, dishing (polishing depressions) tends to occur in the part which is easy to polish. Due to the nature of polishing in the CMP method, this history of imperfections or dishing is particularly significant when the imperfections or parts which are easy to polish have a large area. Specifically, in polishing by the CMP method, although small imperfections can be flattened relatively well, undulations (global undulations) remain over a large area when a large pattern (usually of the order of several &mgr;m or more) is repeated, for example, and so it is difficult to flatten the surface completely.
However, a method has been proposed where a dummy pattern is disposed in regions where there are large patterns or where there is a wide pattern interval. In this method, the pattern interval is decreased due to the dummy pattern, so that the aforesaid wide area (global) dishing or undulations are suppressed. For example, in Japanese Unexamined Patent Publication No. Hei 10-335333 (1998) (Koho) (U.S. Ser. No. 09/050,416, Mar. 31, 1998), a technique is disclosed wherein a dummy pattern is disposed in a region with a wide pattern interval to improve the flatness of the surface of an insulating film which fills the pattern.
SUMMARY OF THE INVENTION
By disposing a dummy pattern in a region where there is a large distance between patterns, so as to decrease the pattern interval, it is possible to deal with the problem of dishing (depressions) or undulations over a wide area. In dishing, the larger the area is the lower the position of the depression in the central part is; and, therefore, by disposing the dummy pattern so as to decrease the area over which dishing occurs, the depth of the depression can be relatively decreased.
Nevertheless, no matter how small the pattern interval is made, dishing cannot be completely eliminated. When the problem surface to be flattened is a single layer, the depression amount is largely improved compared with the dishing which occurs in large area parts, but when the layer to be flattened is a laminate of plural layers, dishing components (depressions) are superimposed due to the positioning of the pattern, and a large amount of dishing occurs in the upper layer. In such a case, there is a decreased tolerance in the focal depth when photolithography is performed on the upper layer in a photolithography step, the overetching amount in an etching step increases, and the yield decreases.
In regions, such as scribe regions, in which elements which become products are not normally formed, a target is formed for an exposure device (such as a stepper or the like) which is used in photolithography. A dummy pattern cannot be disposed on the periphery of this target as it is necessary to recognize the pattern. The area of the target is normally of the order of several &mgr;m or more. Therefore, if a dummy pattern is not disposed in this large (large area) pattern region, dishing occurs as described above. In the prior art, as this large area pattern was formed in a scribe region and not in a product region, this was not considered to be a problem. However, the dishing in the scribe region also affects the product region, and since the tolerance of focal depth in the exposure step is becoming more critical due to the trend towards higher detail, the decreased flatness of the product region (in particular the periphery) is a matter of concern.
It is therefore an object of this invention to suppress dishing on a surface to be flattened comprising a laminate of plural layers.
It is another object of this invention to improve surface flattening in a pattern region having a large area for optical position detection such as a target.
It is still another object of this invention to improve a surface to be flattened comprising plural layers, or the flattening of a pattern of large area such as a target, thereby improving the patterning margin in a photolithography step and etching step.
The aforesaid and other objects of this invention and novel features thereof will become apparent from the following description and appended drawings.
Of the inventive features disclosed in the present application, the most typical can simply be summarized as follows.
A semiconductor integrated circuit device according to this invention comprises a semiconductor substrate having a semiconductor element formed on a main surface, a first pattern comprising a dummy pattern formed on the main surface or on one of the layers on the main surface, and a second pattern formed on an upper layer of the first pattern and comprising a pattern which serves as a target for optical pattern recognition, the pattern which serves as a target for optical pattern recognition being enclosed within the flat shape of the dummy pattern. According to this semiconductor integrated circuit device, the dummy pattern is disposed underneath the pattern used for optical pattern recognition, so that a decrease of the overall flatness in this pattern region is suppressed.
The first pattern may contain another dummy pattern having a smaller area than the dummy pattern. The dummy pattern and another dummy pattern may also be formed in a scribe region. Further, other dummy patterns may be formed in a product region and a scribe region.
The dummy pattern is formed with an area equal to or greater, than a pattern prohibition region on the periphery of the pattern used for optical pattern recognition. Therefore, a decrease in the recognition rate of optical pattern recognition of this pattern is prevented.
The first pattern has patterning dimensions of the same order as the design rule of the semiconductor elements and contains another dummy pattern having a smaller area than the dummy pattern, but the other dummy pattern is not disposed in the pattern prohibition region. In this way, by disposing a small area dummy pattern, except in the
Chakihara Hiraku
Ichise Teruhisa
Kaminaga Michimoto
Uchiyama Hiroyuki
Antonelli Terry Stout & Kraus LLP
Hitachi, ltd.
Nguyen Cuong Quang
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