Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-11
2004-04-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06721932
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of designing the same, and more particularly, it relates to a semiconductor integrated circuit device including a circuit block having a hierarchical structure and a method of designing the same.
2. Description of the Prior Art
In recent years, a semiconductor integrated circuit device applied to an electronic device or the like must be miniaturized, weight-saved, power-saved and reduced in cost. In consideration of such requirements, a system LSI prepared by providing a memory and various types of logic circuits on a single chip is developed. A method of designing a semiconductor integrated circuit device with reference to a basic unit of a circuit block, also referred to as a functional block (IP), including a number of cells implementing certain functions is generally known as a design technique corresponding to such a system LSI. In relation to such a method of designing a semiconductor integrated circuit device with reference to the basic unit of the circuit block, a method of designing a semiconductor integrated circuit device by creating a hierarchical structure with reference to the basic unit of the circuit block is also known.
In the aforementioned method of designing a semiconductor integrated circuit device by creating the hierarchical structure with reference to the basic unit of the circuit block, a method using a gated clock employing a gate turning on a clock only when necessary is also proposed as a method of reducing power consumption. This gated clock is described in “Technical White Paper of Low-Power LSIs”, extra issue of Nikkei Microdevices by Nikkei Business Publications, Inc., 1994, p. 80, for example.
Further, Japanese Patent Laying-Open No. 2000-123059, for example, discloses a method of designing a semiconductor integrated circuit device with reference to a basic unit of the aforementioned circuit block. This gazette discloses a design method reducing power consumption by sharing parts sharable between blocks in a single hierarchy.
However, the aforementioned gazette discloses only a design method related to reduction of power consumption in a single hierarchy, with no disclosure of a design method related to reduction of power consumption in a hierarchical structure. In general, therefore, it is difficult to provide a simple design method for reducing power consumption in relation to design of a semiconductor integrated circuit device including a plurality of circuit blocks having a hierarchical structure. Particularly when the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies, the hierarchical structure is so complicated that it is difficult to provide a simple design method related to reduction of power consumption. In general, therefore, it is difficult to design a semiconductor integrated circuit device of low power consumption by a simple method if the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies.
When the semiconductor integrated circuit device has a hierarchical structure, the structure of a gated clock employed for reducing power consumption is generally disadvantageously complicated. Particularly when the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies, the hierarchical structure is complicated to result in remarkable complicatedness of the structure of the gated clock. In order to change the design of the semiconductor integrated circuit device for changing the combination of the circuit blocks or the hierarchical structure, further, the structure of the gated clock must be newly redesigned in general. In general, therefore, it is difficult to simply design the structure of the gated clock for changing the design of the semiconductor integrated circuit device.
SUMMARY OF THE INVENTION
An object of the present invention is to readily obtain a semiconductor integrated circuit device of low power consumption by selecting a gated clock for reducing power consumption by a simple method when the semiconductor integrated circuit device has a hierarchical structure.
Another object of the present invention is to provide a method of designing a semiconductor integrated circuit device capable of readily selecting a gated clock for reducing power consumption when the semiconductor integrated circuit device has a hierarchical structure.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises a plurality of circuit blocks having a hierarchical structure including at least three hierarchies and outputting an operation control signal from each upper hierarchy to each lower hierarchy, and employs at least one gated clock selected from a group including at least three gated clocks consisting of at least two gated clocks generated by employing at least two operation control signals output to different hierarchies as gate signals and a prescribed gated clock input in a circuit block of the most significant hierarchy as a gated clock input in a circuit block of a lower hierarchy below a third hierarchy among the plurality of circuit blocks. The semiconductor integrated circuit device of the present invention includes a semiconductor integrated circuit device in the designing stage.
According to the aforementioned structure, the semiconductor integrated circuit device according to the first aspect mechanically simply decides a plurality of gated clocks for reducing power consumption on the basis of the operation control signal and the prescribed gated clock input in the circuit block of the most significant hierarchy. When at least one gated clock satisfying a prescribed circuit constraint is selected from the plurality of gated clocks, a semiconductor integrated circuit device of low power consumption can be readily obtained.
In the semiconductor integrated circuit device according to the aforementioned first aspect, a master clock is preferably input in a circuit block of a first hierarchy defining the most significant hierarchy among the plurality of circuit blocks as the gated clock, and a circuit block of a second hierarchy defining a lower hierarchy for the first hierarchy preferably receives either a gated clock generated by employing an operation control signal output from the circuit block of the first hierarchy to the second hierarchy as a gate signal or the master clock. According to this structure, the gated clocks input in the circuit blocks of the first and second hierarchies for reducing power consumption can be readily selected.
In the semiconductor integrated circuit device according to the aforementioned first aspect, at least one gated clock satisfying a prescribed circuit constraint among the plurality of gated clocks included in the aforementioned group is preferably input in the circuit block below the third hierarchy. According to this structure, at least one gated clock satisfying the prescribed circuit constraint is input in the circuit block below the third hierarchy, whereby optimized gated clocks satisfying the prescribed circuit constraint can be readily supplied in the circuit blocks having the hierarchical structure. In this case, the prescribed circuit constraint preferably includes such a constraint that a single gated clock operates at least a prescribed number of flip-flops. According to this structure, it is possible to select a gated clock more suitable for low power consumption than a case of flip-flops operating in excess of the prescribed number. Thus, a semiconductor integrated circuit device capable of further reducing power consumption can be obtained.
In the semiconductor integrated circuit device according to the aforementioned aspect, the circuit block of the lower hierarchy preferably operates only during operation of the circuit block of the upper hierarchy.
In the semiconductor integrated circuit device according to the aforementioned first aspect, each
Ohyama Tatsushi
Yamauchi Hideki
Lin Sun James
Sanyo Electric Co,. Ltd.
Smith Matthew
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