Semiconductor integrated circuit device including an ESD...

Details Semiconductor integrated circuit device including an ESD... Semiconductor integrated circuit device including an ESD...

2002-09-24

2004-08-10

Ngo, Ngan V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S357000, C257S360000, C257S361000, C257S362000, C257S363000

Reexamination Certificate

active

06774438

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuit devices including an electrostatic discharge (ESD) protection circuit and more particularly relates to a semiconductor integrated circuit device including an ESD protection circuit with an improved ESD protection capability for input or output circuit protection.
In recent years, the degree of integration of semiconductor integrated circuit devices has been increasing along with the technical advancements in the fabrication process, i.e., a reduction in size and an increase in density. Along with this, such devices have become more vulnerable to damages caused by electrostatic discharge (hereinafter referred to as “surge”). For example, there are high possibilities that a surge entering through an external connection pad damages an element such as an input circuit, an output circuit, an input and output circuit or an internal circuit, or causes the characteristics of such an element to deteriorate. For this reason, the external connection pad is often provided with a protection circuit for protecting the input circuit, the output circuit, the input and output circuit or the internal circuit from a surge.
FIG. 3
is an electric circuit diagram illustrating the configuration of an output circuit and other elements around the output circuit in a known semiconductor integrated circuit device including an electrostatic discharge protection circuit. As shown in
FIG. 3
, the semiconductor integrated circuit device includes an external connection pad
101
, an electrostatic discharge protection circuit
102
, an output circuit
103
, an output pre-buffer circuit
104
, and an internal circuit
121
, and is configured so that the output circuit
103
is protected by the electrostatic discharge protection circuit
102
from a surge entering through the external connection pad
101
.
The electrostatic discharge protection circuit
102
is provided between the external connection pad
101
and the output circuit
103
, and includes a PMIS transistor
105
, an NMIS transistor
106
, a first resistor
107
, and a second resistor
108
. The PMIS transistor
105
includes: a source connected to a power supply line
119
for supplying a power supply voltage VDD; a gate connected to the power supply line
119
via the first resistor
107
; a drain connected to the external connection pad
101
; and a substrate region (n well) connected to the power supply line
119
. The NMIS transistor
106
includes: a source connected to a ground line
120
for supplying a ground voltage VSS; a gate connected to the ground line
120
via the second resistor
108
; a drain connected to the external connection pad
101
; and a substrate region (p well) connected to the ground line
120
.
The output circuit
103
is provided between the electrostatic discharge protection circuit
102
and the output pre-buffer circuit
104
, and includes a PMIS transistor
111
and an NMIS transistor
112
. The PMIS transistor
111
includes: a source connected to the power supply line
119
; a gate connected to an output part of a first pre-buffer
115
in the output pre-buffer circuit
104
; a drain connected to the external connection pad
101
; and a substrate region (n well) connected to the power supply line
119
. The NMIS transistor
112
includes: a source connected to the ground line
120
; a gate connected to an output part of a second pre-buffer
117
in the output pre-buffer circuit
104
; a drain connected to the external connection pad
101
; and a substrate region (p well) connected to the ground line
120
.
The output pre-buffer circuit
104
for amplifying an output signal from the internal circuit
121
is provided between the internal circuit
121
and the output circuit
103
, and includes a first pre-buffer circuit
116
and a second pre-buffer circuit
118
. The first pre-buffer circuit
116
includes the first pre-buffer
115
in the final stage and the second pre-buffer circuit
118
includes the second pre-buffer
117
in the final stage. The first pre-buffer circuit
116
and the second pre-buffer circuit
118
each include a plurality of pre-buffers according to the degree of amplification by which an output signal from the internal circuit
121
is to be amplified. In the first pre-buffer circuit
116
, each of the pre-buffers includes a voltage supply part connected to the power supply line
119
and a ground part connected to the ground line
120
, the output part of the final-stage pre-buffer is connected to the gate of the PMIS transistor
111
in the output circuit
103
, and an input part of the pre-buffer in the initial stage is connected to the internal circuit
121
. In the second pre-buffer circuit
118
, each of the pre-buffers includes a voltage supply part connected to the power supply line
119
and a ground part connected to the ground line
120
, the output part of the final-stage pre-buffer is connected to the gate of the NMIS transistor
112
in the output circuit
103
, and an input part of the pre-buffer in the initial stage is connected to the internal circuit
121
. The first and second pre-buffer circuits
116
and
118
are configured so that two high and low output signals or two identical output signals are output from the output part of the final-stage first pre-buffer
115
in the first pre-buffer circuit
116
and from the output part of the final-stage second pre-buffer
117
in the second pre-buffer circuit
118
.
With the conventional semiconductor integrated circuit device having such a configuration, a surge applied between the power supply line
119
and the external connection pad
101
is absorbed by breakdown of the PMIS transistor
105
, and a surge applied between the ground line
120
and the external connection pad
101
is absorbed by breakdown of the NMIS transistor
106
. Thus, it is possible to effectively protect the output circuit
103
from a surge entering from the outside through the external connection pad
101
.
Incidentally, semiconductor integrated circuit devices need to meet an ESD test standard because it is required to assure the users of a certain surge breakdown withstand voltage. In recent years, a human body model (HBM) ESD test standard such as an MIL standard has become the global standard as an ESD test standard, and semiconductor integrated circuit devices need to meet the HBM test standard.
FIG. 4A
is a circuit diagram illustrating an evaluation circuit for conducting an ESD test based on the HBM test standard, and
FIG. 4B
is a waveform diagram illustrating HBM discharge waveform specifications of the MIL standard.
As illustrated in
FIG. 4A
, the evaluation circuit includes a charging power supply
150
and a discharging resistor
153
having a resistance of R=1.5 k&OHgr;, which are arranged respectively in two circuits (the left-side circuit and the right-side circuit illustrated in FIG.
4
A). The two circuits are arranged in parallel with respect to a charging/discharging capacitor
151
having a capacitance of C=100 pF. A selector switch
152
is connected to one electrode of the charging/discharging capacitor
151
, and the selector switch
152
is used to selectively connect said one electrode of the charging/discharging capacitor
151
either to a high-voltage portion of the variable-voltage charging power supply
150
or to the discharging resistor
153
. Moreover, the other electrode of the charging/discharging capacitor
151
is connected to a low-voltage portion of the charging power supply
150
in the left-side circuit illustrated in FIG.
4
A and is connected to the discharging resistor
153
in the right-side circuit illustrated in
FIG. 4A. A
subject device
154
is placed in the right-side circuit illustrated in
FIG. 4A
between the other electrode of the charging/discharging capacitor
151
and the discharging resistor
153
so that an ESD test is conducted on the subject device
154
.
In order to conduct an ESD test using the evaluation circuit, said one electrode of the charging/discharging capacito

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