Semiconductor integrated circuit device including...

Details Semiconductor integrated circuit device including... Semiconductor integrated circuit device including...

2005-05-17

2005-05-17

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000, C714S733000, C714S734000, C714S738000, C365S200000, C365S201000

Reexamination Certificate

active

06895537

ABSTRACT:
Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

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Nordholz, P et al. ‘A defect-tolerant word-oriented static RAM with built-in self-test and self-reconfiguration,’ IEEE International Conference on Proceedings, Innovative Systems in Silicon, Oct. 9-11, 1996, On pp.: 124-132.*
“An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264,” by Bhavsar, ITC International Test Conference (1999), pp. 311-318.
“Built-In Self-Test for GHz Embbedded SRAMs Using FLEXIBLE Pattern Generator and New Repair Algorithm,” by Nakahara et al., ITC International Test Conference (1999), pp. 301-310.

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