Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-22
2001-02-20
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S206000, C365S207000, C365S149000, C365S230060, C365S226000, C365S228000, C365S051000, C365S063000
Reexamination Certificate
active
06191990
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The Present invention relates to a semiconductor integrated circuit device, and primarily to a technique which is useful for a large-scale integrated circuit incorporating a dynamic RAM (random access memory) and an associated memory control logic circuit.
BACKGROUND OF THE INVENTION
Based on a study conducted after the present invention was made, the inventors of the present invention have discovered the presence of techniques described in Japanese laid-opened Patent Publications No. 10-74908, No. 3-280298 and No. 2-177082 which pertain to power noise suppression, as will be explained in the following. These patent publications described techniques for the suppression of power noises which arise during the amplifying operation of sense amplifiers which detect small signals read out of dynamic memory cells. Specifically, the technique described in Japanese laid-opened Patent Publication No. 10-74908 pertains to the disposition of capacitors, which are formed by the same process as that of storing capacitors of memory cells, between the power lines of the sense amplifiers. However, there is no description at all in this patent publication on power noises created by the main amplifiers for amplifying the outputs of sense amplifiers, which is a feature with which the present invention is concerned.
The inventors of the present invention have studied a scheme for the speed-up of the readout operation of the storage section, which employs dynamic memory cells for accomplishing a large storage capacity, based on the provision of a buffer memory formed of static memory cells so that data comprising a large number of bits are read out of the storage section to the buffer memory at once, thereby carrying out a data transaction with the outside through the buffer memory. Namely, the buffer memory is operated as a cache memory, so that the memory operation is sped up when seen from the outside of the semiconductor integrated circuit device.
In order to read out data comprising a large number of bits from dynamic memory cells, many main amplifiers are required in correspondence to the individual bits. The main amplifier, which amplifies the amplified signal from the sense amplifier, has a larger amplitude input signal as compared with a sense amplifier. It, at the same time, needs to deal with relatively large currents for the high-speed operation as compared with a sense amplifier. From the opposite viewpoint, it is necessary for the sense amplifier to minimize the operation current in order to sense stably a small signal which is read out to a bit line indicative of the presence or absence of information charges accumulated in a small storage capacitor.
Specifically, a signal which is read out to a bit line is a small voltage near the middle of the operation voltages, and the input of such a small voltage near the middle voltage to the sense amplifier of a CMOS latch configuration causes both the n-channel and p-channel amplifying MOSFETs to become conductive. Therefore, increasing the current for the sensing operation will result in the arising of large penetrating currents through the on-state amplifying MOSFETS. Due to the amplifying operation of the CMOS latch circuit based on the positive feedback of the output signals to the inputs, the readout signal voltage will fluctuate due to the influence of the penetrating currents, resulting in the high possibility of a read error.
Accordingly, the scheme of the above-mentioned patent publication for the speed-up of the sense amplifier, which is based on the setting of such a large operation current as to invoke a problem of noises created by its own amplifying operation and on the absorption of the noises by the capacitance, necessitates the provision of noise suppressing capacitors for many sense amplifiers provided in correspondence to rows of the memory cell array in the word line direction, and it is not advantageous from the viewpoint of utilizing the feature of dynamic memory cells which enables high-density integration. Instead, it is more rational to adopt the easier method of simply minimizing the operation current of the sense amplifier for primarily stabilizing the sense amplifier operation.
The main amplifier, which amplifies the amplified signal from the sense amplifier and deals with a larger amplitude input signal as compared with the sense amplifier, is capable of performing a stable and fast amplifying operation based on larger currents as compared with the sense amplifier. It was found, however, that when it is intended to read out memory cells of many bits at one time for a high-speed data transaction with the outside, in which case a huge number of main amplifiers are needed as compared with general-purpose dynamic RAMs, there emerges a problem of a malfunctioning of the logic circuit in the peripheral address selecting circuit and buffer memory.
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device which incorporates a dynamic PAM, and is capable of accomplishing high-density integration and fast and stable operation. These and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
Briefly, the present invention resides typically in a semiconductor integrated circuit device having amplifying MOSFETs of sense amplifiers for amplifying small voltages read out of dynamic memory cells onto bit lines, a memory array including column switch MOSFETs for selecting bit lines, a read/write section including main amplifiers for reading stored data out of memory cells selected by the column switch, and a logic circuit section which implements the input/output operation of data with the read/write section, wherein two capacitors, each having a first electrode which corresponds to a plate electrode with the same structure, of storage capacitors of the dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors, are arranged in serial connection, disposed contiguously to the read/write section, and connected between the operation voltage lines of the read/write section.
REFERENCES:
patent: 5848001 (1998-12-01), Kim
patent: 5862091 (1999-01-01), Bion et al.
patent: 6028802 (2000-02-01), Nishikawa
patent: 2177082 (1990-07-01), None
patent: 3280298 (1991-12-01), None
patent: 10074908 (1998-03-01), None
Itoh Nobutaka
Kobayashi Toru
Kusunoki Mitsugu
Miyaoka Shuichi
Nakayama Michiaki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tran Andrew Q.
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