Semiconductor integrated circuit device having spare word lines

Details Semiconductor integrated circuit device having spare word lines Semiconductor integrated circuit device having spare word lines

2002-03-13

2003-02-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S203000, C365S205000

Reexamination Certificate

active

06519193

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device having spare word lines.
2. Description of the Background Art
Among semiconductor integrated circuit devices, a dynamic semiconductor memory device (hereinafter, referred to as DRAM (dynamic random access memory)), for example, has a plurality of spare word lines in addition to normal word lines as redundancy technology.
For example, when one of a plurality of memory cells connected to a normal word line becomes defective, the DRAM having spare word lines replaces the normal word line connected to the defective memory cell with a spare word line. When a normal word line itself becomes defective due to some factor, the DRAM replaces the defective normal word line with a spare word line.
When a defective normal word line is replaced with a spare word line, the potential on the replaced defective normal word line is normally fixed to the ground potential. As a result, the replaced defective normal line will not be accessed, and therefore will not affect the sense amplifier operation.
However, in the case where the replaced defective normal word line is short-circuited with high resistance to a bit line BL or ZBL connected to a sense amplifier, it affects the sense amplifier operation.
FIG. 22
is a schematic block diagram showing a region in a memory cell array of the DRAM.
Referring to
FIG. 22
, each memory cell MC is connected to a word line WL of a corresponding row. Each memory cell MC includes an N-channel access MOS (metal oxide semiconductor) transistor QN
1
and a storage capacitor C
1
.
The memory cell array includes normal word lines NWL for use in normal operation, and spare word lines SWL used as a substitute for a defective normal word line NWL.
The memory cell array further includes bit line pairs BL, ZBL. A sense amplifier SA and an equalizer EQ are connected to the bit line pairs BL, ZBL.
It is now assumed that, in the memory cell array of
FIG. 22
, a normal word line NWL
0
is replaced with a spare word line SWL
0
due to some factor, and the replaced defective normal word line NWL is short-circuited with high resistance to a bit line BL.
During a precharge period, the bit line pairs BL, ZBL are held at a precharge potential equal to Vcc/2 (hereinafter, referred to as VBL potential level) by the equalizer EQ.
However, since the bit line BL is short circuited with high resistance to the defective normal word line NWL
0
, the VBL potential on the bit line pair BL, ZBL leaks to the short-circuited defective normal word line NWL
0
. As a result, the VBL potential on the bit line pair BL, ZBL falls from the intermediate potential.
FIG. 23
is a timing chart illustrating the operation of reading L level in the memory cell (which is a part of the sense amplifier operation) in the case where the bit line BL is short-circuited with high resistance to the defective normal word line NWL
0
in FIG.
22
.
Referring to
FIG. 23
, since the bit line BL is short-circuited with high resistance to the defective normal word line NWL
0
, the VBL potential falls from the intermediate potential during a precharge period. The sense amplifier SA starts sensing operation after the precharge period. Since the VBL potential is lower than the normal level, it is difficult for the sense amplifier SA to read L level from the memory cell.
The relation between the VBL potential level and the L level read potential &Dgr;is given by the following equation:
&Dgr;
V=−VBL
/(1
+Cb/Cs
)  (1).
In the equation (1), Cb is a capacitance of the memory cell MC, and Cs is a stray capacitance of the bit line BL, ZBL.
According to the equation (1), the read potential &Dgr;V reduces as the VBL potential level falls to a lower level, thereby possibly causing defective sense amplifier operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit device capable of stably conducting sensing operation even when a defective normal word line replaced with a spare word line is short-circuited to a bit line.
A semiconductor integrated circuit device according to the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of normal word lines arranged respectively corresponding to the memory cell rows; a plurality of spare word lines arranged respectively corresponding to the memory cell rows, for substituting for a defective normal word line of the plurality of normal word lines; a plurality of bit line pairs arranged respectively corresponding to the memory cell columns; a equalizer circuit for, precharging the plurality of bit line pairs to a prescribed potential; a sense amplifier circuit for amplifying a potential difference in the bit line pair; a spare row determination circuit for replacing the defective normal word line with the spare word line; and a word line precharge circuit for precharging the defective normal word line replaced by the spare row determination circuit to the prescribed potential.
Preferably, the word line precharge circuit includes a word line precharge determination circuit for determining whether the replaced defective normal word line is to be precharged to the predetermined potential or not, and a word line potential level control circuit for controlling a potential level on the replaced defective normal word line in response to the determination result of the word line precharge determination circuit.
Thus, the replaced defective normal word line has the same potential as that of the bit line pair. Therefore, the potential on the bit line pair will not be reduced during the precharge period.
Preferably, the word line precharge determination circuit outputs a determination signal to the word line potential level control circuit in response to a control signal for controlling operation of the sense amplifier circuit.
Preferably, the word line precharge circuit renders the replaced defective normal word line in a high impedance state during operation of the sense amplifier circuit.
Thus, the potential on the replaced defective normal word line will not affect the potential on the bit line pair during sense amplifier operation, whereby the sense amplifier operation is facilitated.
Preferably, the word line precharge circuit reduces the potential on the replaced defective normal word line during operation of the sense amplifier circuit.
Thus, the potential on the replaced defective normal word line will not affect the potential on the bit line pair during sense amplifier operation, whereby the sense amplifier operation is facilitated.
According to the present invention, the potential level on the bit line BL or ZBL short-circuited to the defective normal word line NWL will not fall from the precharge potential level during the precharge period. As a result, the sense amplifier operation is stabilized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5796271 (1998-08-01), Kumar
patent: 6144599 (2000-11-01), Akita et al.
patent: 6333877 (2001-12-01), Nagaoka et al.

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