Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-01-22
2003-01-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S083000
Reexamination Certificate
active
06504402
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit composed of scaled MOS transistors, and more particularly to a circuit suitable for high-speed and low power operation and an electronic device using the same.
As the size of MOS transistors is scaled down, the breakdown voltage thereof is lowered as stated, for example, in the 1989 International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp. 188-192 (May 1989). Accordingly, the operating voltage thereof has to be lowered. In particular, the operating voltage is lowered even more for the purpose of achieving low power consumption for semiconductor devices used in a battery-operated portable equipment and the like.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit capable of operating at high speed and with low power consumption even when the size of MOS transistors is scaled down.
It is another object of the present invention to provide an electronic device capable of operating at high speed and with low power consumption and suitable for being battery powered drive even when the size of MOS transistors is scaled down.
To decrease power consumption for an integrated circuit having MOS transistors, it is necessary to lower the threshold voltage V
T
of the transistor in accord with the lowering of the operating voltage in order to maintain a high-speed operation. This is due to the fact that the operating speed is governed by the effective gate voltage of the MOS transistor, i.e., a value obtained by subtracting V
T
from the operating voltage, and the larger this value becomes, the higher the speed becomes. For example, a typical value of a threshold voltage of a transistor having a channel length of 0.25 &mgr;m and operating at 1.5 V is anticipated to be 0.35 V according to the above-mentioned document. According to a well-known scaling law, the typical value of the threshold voltage becomes approximately 0.24 V when it is assumed that the operating voltage is 1 V. If V
T
is brought down to approximately 0.4 V or lower, however, it becomes no longer possible to turn the transistor completely off and a D.C. current starts to flow through it due to the sub-threshold characteristics (tailing characteristics) of the MOS transistor as described hereafter. Thus, this current becomes a serious issue in the practical operation of a device having MOS transistors at 1.5 V or lower.
A conventional CMOS inverter shown in
FIG. 49
will be described. Ideally, an N-channel MOS transistor M
N
is turned off when an input signal IN is at a low level (=V
SS
), and a P-channel MOS transistor M
P
is turned off when IN is at a high level (=V
CC
), thus no current flows in either case. When V
T
of the MOS transistor becomes low, however, the subthreshold current can no longer be disregarded.
As shown in
FIG. 50
, a drain current I
DS
in a subthreshold region is in proportion to an exponential function of a gate-source voltage V
GS
and is expressed by the following expression.
I
DS
=
I
o
·
W
W
o
·
10
V
GS
-
V
T
S
(
1
)
Where, W indicates a channel width of the MOS transistor, I
O
and W
O
indicate a current value and a channel width when V
T
is defined, and S indicates a subthreshold swing (the gate-voltage swing needed to reduce the current by one decade). Thus, a subthreshold current:
I
L
=
I
o
·
W
W
o
·
10
-
V
T
S
(
2
)
flows even when V
GS
=0. Since V
GS
=0 in the transistor in an off-state of the CMOS inverter shown in
FIG. 49
, the current I
L
mentioned above will flow from the high power supply voltage V
CC
toward the low power supply voltage V
SS
which is at ground potential, even at the time of non-operation.
This subthreshold current increases exponentially from I
L
to I
L
′ when the threshold voltage is lowered from V
T
to V
T
′ as shown in FIG.
50
.
As is apparent from the above expression (2), it is sufficient either to increase V
T
or to decrease S in order to reduce the subthreshold current. However, the former method brings about a lowering of the speed due to a lowering of the effective gate voltage. In particular, when the operating voltage is lowered with the scale-down of the breakdown voltage, the decrease in speed becomes notable and the advantages of scaled down fabrication can no longer be put to practical use, which is not preferable. Further, the latter method is difficult to apply for room temperature operation because of the following reasons.
The subthreshold swing S is expressed by the capacitance C
OX
of a gate insulator and the capacitance c
D
of a depletion layer under the gate as follows.
S
=
kT
ln
10
q
[
1
+
C
D
C
ox
]
(
3
)
Where, k indicates the Boltzmann constant, T indicates absolute temperature, and q indicate the elementary charge. As is apparent from the above expression, S≧KT 1n 10/q irrespective of C
OX
and C
D
, thus it is difficult to bring it to 60 mV or lower at room temperature.
The substantial D.C. current of a semiconductor integrated circuit composed of a plurality of MOS transistors increases remarkably due to the phenomenon described above. Namely, since V
T
has to be made lower as the operating voltage is lowered at a constant operating speed, the situation becomes more serious when the operation is performed at a lower voltage. At the time of operation at a high temperature in particular, V
T
becomes lower and S becomes larger. Therefore, this problem becomes even more serious. In the times of downsizing of computers or the like for the future when low power consumption is important, the increase of the subthreshold current is a substantial issue. In particular, in an electronic device which is desired to be operated by one power cell of a level of 0.9 to 1.6 V, it is also very important to cope with the increase of the current.
In order to solve the above-described problems, according to the present invention, control circuit means for controlling the supply of a large current and a small current is inserted between the source of a MOS transistor and the power supply so as to apply a current to the MOS transistor circuit by switching these currents in accordance with their use. For example, a large current is supplied when high-speed operation is required, and a small current is supplied when low power consumption is required.
Since high-speed operation is required at time of normal operation, a large current is supplied to the MOS transistor circuit from the current supply means so as to make high-speed operation possible. At this time, a D.C. current flows in the MOS transistor circuit as described previously, which, however, is sufficiently small normally as compared with the operating current, i.e., charging and discharging current of a load, thus causing no problem.
On the other hand, since low power consumption is required at the time of standby, the supplied current is changed over to a small current so as to restrain the subthreshold current. At this time, a logic voltage swing of a MOS transistor circuit generally may become smaller than that at the time of supplying a large current because the current is limited, but there is no problem in so far as ensuring the logic level.
As described above, it is possible to realize a high-speed and low power consuming MOS transistor circuit and an electronic device composed of the same according to the present invention.
Besides, the present invention has been described with a MOS semiconductor integrated circuit device as an example, but the present invention is applicable to a metal insulator semiconductor (MIS) integrated circuit device in general.
REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4624006 (1986-11-01), Rempfer et al.
patent: 4797580 (1989-01-01), Sunter
patent: 4816705 (1989-03-01), Ohba et al.
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4859870 (1989-08-01), Wong et
Aoki Masakazu
Horiguchi Masashi
Itoh Kiyoo
Kawahara Takayuki
Sakata Takeshi
Cho James H.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tokar Michael
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