Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-16
2004-03-23
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C712S010000
Reexamination Certificate
active
06711724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device, and to a semiconductor integrated circuit device, and more particularly to a method of designing a semiconductor integrated circuit device capable of reducing overhead such as clock skews and clock jitters when designing a pipeline in an integrated circuit device, and to a configuration of a semiconductor integrated circuit device manufactured according to such designing method.
2. Description of the Background Art
In an LSI large scale integrated circuit), a synchronous multi-stage pipeline for processing/transferring a signal synchronously with a clock signal so as to transfer the signal/data at high speed, is widely used. In constituting such a synchronous multi-stage pipeline, flip-flops or latches are normally used as transfer circuits.
FIG. 9
is a diagram showing an example of the configuration of a two-stage pipeline constituted by flip-flops. In
FIG. 9
, the two-stage pipeline includes a flip-flop circuit FF
01
which transfers an input signal IN synchronously with a clock signal CLK
01
, a logic circuit LG
1
which performs a predetermined logic processing on the signal applied from flip-flop circuit FF
01
and outputs a resultant signal, a flip-flop circuit FF
02
which transfers the output signal of logic circuit LG
1
synchronously with a clock signal CLK
02
, a logic circuit LG
2
which performs a predetermined logic processing on the signal applied from flip-flop FF
02
and outputs a resultant signal, and a flip-flop circuit FF
03
which transfers the output signal of logic circuit LG
2
synchronously with a clock signal CLK
03
and generates an output signal/data OUT.
Since logic circuits LG
1
and LG
2
each perform a logic processing on the received signal for outputting, logic circuits LG
1
and LG
2
have logic delays L
01
and L
02
in the propagation of the signals, respectively.
Normally, logic circuits LG
1
to LG
2
each receive a plurality of signals and performs a logic processing. In the description given hereinafter, though not particularly mentioned, a flip-flop circuit FF transfers one or a plurality of signals. The number of signals transferred by flip-flop circuit FF is determined according to the configuration of a logic circuit LG arranged at the subsequent stage.
Flip-flop circuit FF
01
has setup time SUP
11
and hold time HLD
11
for clock signal CLK
01
. In addition, flip-flop circuit FF
01
has output delay time TPD
11
since a trigger edge of clock signal CLK
01
is applied until a valid signal is outputted.
Flip-flop circuit FF
02
has setup time SUP
12
and hold time HLD
12
and output delay time TPD
12
.
Flip-flop circuit FF
03
has setup time SUP
13
and hold time HLD
13
and output delay time TPD
13
.
Further, fixed skews due to uncertain factors of clock signals, as described later, exist for the clock signals applied to flip-flop circuits FF
01
to FF
03
, respectively.
FIG. 10
is a diagram showing output delay time TPD, setup time SUP and hold time HLD shown in FIG.
9
.
FIG. 10
shows parameters in a case where flip-flop circuits FF
01
to FF
03
are each a rising edge trigger type flip-flop that latches and outputs a signal applied at the rising edge of clock signal CLK.
Setup time SUP is a time period for which input signal SIN is kept in a definite state with respect to the rising edge of clock signal CLK. Hold time HLD is a time period required for input signal SIN to be kept in a definite state since the rising edge of clock signal CLK. Output delay time TPD is a time period required since clock signal CLK rises until the output signal SOUT of the flip-flop circuit is made definite.
Normally, setup time SUP is determined under the worst condition for the operating parameters of transistors which constitute a flip-flop. Hold time HLD is calculated using the best operating parameters of the transistors which constitute the flip-flop.
Clock signal CLK has a period TK.
As shown in
FIG. 11
, clock signals CLK
01
to CLK
03
are applied from a clock distribution circuit
110
which receives a clock signal CLK
0
generated from a clock generation circuit
100
. Clock distribution circuit
110
transfers applied clock signal CLK
0
to the respective the flip-flop circuits in the pipeline.
Clock generation circuit
100
is constructed by, for example, a PLL (phase locked loop), and generates internal clock signal CLK
0
synchronized in phase with an external clock signal such as a system clock. Clock distribution circuit
110
takes various configurations such as a tree-like clock network and a fishbone type clock distribution circuit according to the configuration of this pipeline.
Clock signals CLK
01
to CLK
03
are transferred through predetermined routes, respectively. Therefore, clock signals CLK
01
to CLK
03
applied to flip-flop circuits FF
01
to FF
03
shown in
FIG. 9
each have clock signal ambiguities referred to as a skew or a jitter. Thus, clock signals CLK
01
to CLK
03
are deviated from an ideal edge of a clock signal.
Here, in the description given hereinafter, “clock skew” is defined as a spatial clock signal deviation caused by process variation and uneven interconnection in clock distribution circuit
110
. Namely, a clock skew indicates the phase deviation of a clock signal caused depending on the positional relationship between each of flip-flop circuits FF
01
to FF
03
and clock generation circuit
100
.
As for the clock skews, fixed factors caused by the unevenness of interconnections and process variations based on layout dependency and uncertain factors dependent on unpredictable process variations and the power supply voltage change, temperature change in clock distribution circuit
110
and other are separately considered. The unevenness of interconnections indicates variations in line width and interconnection length and such. Layout dependent process variations indicate the variations of operating characteristics due to the variations of impurity concentration dependent on the layout in transistors constituting a repeater which is included in clock distribution circuit
110
and which transmits the clock signal.
A “clock jitter” is defined as a temporal clock signal deviation caused by the power supply voltage fluctuation, temperature fluctuation or the like in clock generation circuit (PLL)
100
. It is, therefore, assumed that only uncertain factors exist for the clock jitters. Since the clock jitter is the temporal deviation of the clock signal, similar clock jitters occur to the respective flip-flop circuits.
Referring back to
FIG. 9
, a clock skew SKW
01
between flip-flop circuits FF
01
and FF
02
and a clock skew SKW
02
between flip-flop circuits FF
02
and FF
03
are fixed factor components of the clock skew. In addition, a clock skew between flip-flop circuits FF
01
and FF
03
is denoted by a reference symbol SKWA, which is also a fixed factor component of the clock skew. The fixed factor of the clock skew can take both positive and negative values. The fixed factor (SKW
01
, SKW
02
) of a skew of a clock signal delayed in phase from a given clock signal has a positive value (cycle time can be made longer with respect to a logic circuit at the preceding stage). Further, the fixed factor of the skew of a clock signal faster in phase than this clock signal takes a negative value.
The clock skew uncertain factor between flip-flop circuits FF
01
and FF
02
is equal to that between flip-flop circuits FF
02
and FF
03
, and these factors are each defined to be an absolute value SKWET. This is because they are uncertain factors and the worst case is always supposed.
Furthermore, the clock jitter between flip-flop circuits FF
01
and FF
02
is equal to that between flip-flop circuits FF
02
and FF
03
, and these jitters are each defined to be an absolute value JTR. It is noted that clock jitter JTR is a value per one cycle TK of the clock signal.
A skew MRG is defined to be the sum of jitter component JTR and clock skew uncertain factor S
Burns Doane , Swecker, Mathis LLP
Whitmore Stacy A
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