Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2002-07-30
2003-10-28
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S201000, C365S185090
Reexamination Certificate
active
06639863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor integrated circuit device with a link element, of which a fuse element is representative.
2. Description of the Background Art
Generally, a fuse element for storing a variety of information required for a prescribed operation is provided within a semiconductor integrated circuit device. For example, such information is obtained according to properties evaluated in an operation test which is conducted after chip manufacturing. Thus obtained information is stored on a chip in a non-volatile manner by blowing fuse elements.
As an example, a configuration will be described, in which, in a semiconductor integrated circuit device having a large scale semiconductor memory, replacement information required for replacing and repairing a defective memory cell to improve production yield is stored by means of fuse elements.
FIG. 5
is a schematic block diagram showing a configuration in which information is stored by fuse elements in a conventional semiconductor integrated circuit device.
Referring to
FIG. 5
, a conventional semiconductor integrated circuit device
100
has a memory array
101
and a laser trimming fuse (hereinafter, simply referred to also as LT fuse) group
102
blowable by a laser input. LT fuse group
102
, in response to an external laser input, stores replacement information for replacing and repairing a defective memory cell in memory array
101
in a non-volatile manner.
In semiconductor integrated circuit device
100
, in order to properly replace and repair defective memory cell to obtain desired effect, LT fuse group
102
has to correctly store the replacement information. In other words, LT fuse group
102
should be properly blown by an external laser input.
It is difficult, however, to directly determine whether LT fuses have been properly blown. That is to say, though it is possible by visual inspection to confirm whether these LT fuses have been optically blown, it is difficult to confirm whether they have been electrically blown.
Therefore, whether LT fuses have been properly blown to correctly store replacement information can be determined only indirectly through an operation test after the fuse blowing process. In other words, successful blowing of LT fuse could be confirmed only by evaluating whether replacement and repairment of a defective memory cell has been properly performed according to replacement information stored by LT fuses, that is, by evaluating operation of the entire semiconductor integrated circuit device.
Consequently, unless an operation test following the fuse blowing process is strictly conducted, a semiconductor integrated circuit device, in which LT fuses have not been properly blown, may be mistakenly determined as non-defective. In other words, it is difficult to simplify an operation test in a subsequent process because whether electrical blowing of LT fuses has been successful or not cannot be directly inspected.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a configuration of a semiconductor integrated circuit device in which direct testing for whether a link element (of which an LT fuse is representative) has been properly blown can be conducted.
A semiconductor integrated circuit device according to the present invention includes an internal circuit for performing a prescribed operation; a plurality of first link elements for storing in a non-volatile manner first information used in the internal circuit in response to an external program input; a confirmation information storing portion to store in a non-volatile manner second information for confirming whether the plurality of first link elements have accurately stored the first information; and an input/output port for externally outputting information stored by the plurality of first link elements and information stored by the confirmation information storing portion in an operation test.
Such a semiconductor integrated circuit device can directly check whether the first link elements have stored prescribed information in a non-volatile manner in response to a given program input. Therefore, the operation test in a subsequent process can be simplified.
A semiconductor integrated circuit device according to another configuration of the present invention includes an internal circuit for performing a prescribed operation; a plurality of first link elements for storing in a non-volatile manner first information used in the internal circuit in response to an external program input; a confirmation information storing portion to store in a non-volatile manner second information for confirming whether the plurality of first link elements have accurately stored the first information; and an arithmetic circuit for externally outputting a determination result based on information stored by the plurality of first link elements and information stored by the confirmation information storing portion in an operation test.
Such a semiconductor integrated circuit device can directly determine whether the first link elements have stored prescribed information in a non-volatile manner in response to a given program input. Therefore, the operation test in a subsequent process can be simplified. In addition, determination result can be output using smaller number of terminals than that of the first and second link elements, desirably only one output terminal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6178125 (2001-01-01), Niiro
patent: 6324103 (2001-11-01), Hiraki et al.
patent: 6404683 (2002-06-01), Yumoto
patent: 2002/0006062 (2002-01-01), Otori et al.
patent: 4-170821 (1992-06-01), None
patent: 4-285798 (1992-10-01), None
Imamura Akira
Koyama Toshiaki
Mabuchi Yasuhiro
Le Toan
Lebentritt Michael S.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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