Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-08-31
2002-11-26
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S203000, C365S201000
Reexamination Certificate
active
06486493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, a system LSI on which a memory is mounted. More particularly the invention relates to a configuration of a test interface circuit for conducting an operation test of a memory in the system LSI.
2. Description of the Background Art
A system LSI such as a logic-merged DRAM obtained by integrating a memory core such as a large-capacity dynamic random access memory (DRAM) and a logic device such as a processor or ASIC (Application Specific Integrated Circuit) on the same semiconductor chip (semiconductor substrate) has been developed. Such a system LSI can realize high data transfer speed which is higher than that of a general DRAM by one or two digits by connecting the logic device and the memory such as a DRAM to each other via an internal data bus having a wide data bit width of 128 to 512 bits.
The DRAM and the logic device are connected to each other via an internal wire, and the internal wire is sufficiently short as compared with a wire on the board and has a small parasitic capacitance. Consequently, large reduction in charging/discharging currents in the internal wire and high-speed signal transmission can be realized. The number of external pin terminals of the logic device can be reduced as compared with a method of connecting an external general DRAM to a logic device. For the reasons, the system LSI such as a logic-merged DRAM greatly contributes to higher performance of information equipment dealing with a large amount of data in a three-dimensional graphics process, image/voice processes, and the like.
In the system LSI such as a logic-merged DRAM, only the logic device is mounted to a terminal via a pad. In the case of conducting an operation test on a memory such as a built-in DRAM, the test has to be carried out via the logic device. In this case, however, the control of the operation test is performed by the logic device, so that a load on the logic device increases. Specifically, in the case of conducting the operation test via the logic device, the following need arises. A command to conduct the operation test on the memory such as a DRAM is given from the outside to the logic device, a control signal for conducting the operation test is supplied from the logic device to the memory, and the test result is outputted to the outside by the logic device.
The operation test on the memory in the system LSI as a logic-mounted DRAM is therefore conducted via the logic device. It is consequently difficult to carry out a test of an operation timing margin or the like on the memory with high accuracy.
From the viewpoint of a program capacity as well, the number of test patterns generated by the logic device is limited, so that a sufficient operation test cannot be conducted. Due to the factors, it is difficult to sufficiently guarantee the reliability of the memory such as a DRAM. When the gate scale increases, a defect occurrence probability of the logic device itself becomes high, so that the reliability of the memory test deteriorates. Consequently, a need for conducting a test directly on the memory such as a DRAM from the outside by a dedicated tester such as a memory tester arises. Such a test is also called a direct memory access test.
FIG. 16
is a diagram schematically showing the configuration of a conventional DRAM-mounted system LSI
900
.
Referring to
FIG. 16
, the system LSI
900
includes: a large-scale logic LG which is coupled to an external pin terminal group LPGA and executes an instructed process; an analog core ACR which is coupled between the large-scale logic device LG and an external pin terminal group APG and performs a process of an analog signal; a DRAM core MCR which is coupled to the large-scale logic LG device via internal wires and stores data necessary for the large-scale logic device LG; and a test interface circuit TIC which disconnects the large-scale logic device LG and the DRAM core MCR from each other and couples an external memory tester to the DRAM core MCR via a test pin terminal group TPG at the time of an operation test. The DRAM core MCR receives a power supply voltage VCC via a power supply pin terminal PST.
The analog core ACR includes a phase locked loop (PLL) circuit for generating an internal clock signal, an analog-to-digital converter for converting an analog signal from the outside into a digital signal, and a digital-to-analog converter for converting a digital signal supplied from the large-scale logic LG to an analog signal and outputting the analog signal.
The DRAM core MCR is a synchronous DRAM (SDRAM) which takes in an operation mode instruction signal and receives/transmits data synchronously with a supplied clock signal.
The large-scale logic LG device includes a memory control unit for executing a process such as an image/voice information process and controlling an access to the DRAM core MCR.
As shown in
FIG. 16
, by providing the test interface circuit TIC, the DRAM core MCR is completely disconnected from the logic device (large-scale logic device LG), so that the DRAM core MCR can be directly accessed via the test pin terminal group TPG. Consequently, the DRAM core MCR can be controlled and monitored directly from the outside by a memory tester or the like. By providing the test interface circuit TIC, according to a direct memory access test, an operation test which is substantially the same as that conducted on a general DRAM (SDRAM) by using a conventional memory tester can be conducted.
FIG. 17
is a diagram showing the configuration of the test interface circuit TIC and its related portion illustrated in FIG.
16
.
Referring to
FIG. 17
, the test pin terminal group TPG includes: a pin terminal for receiving a test clock signal TCLK; a pin terminal for receiving a test control signal TCMD which designates a test operation mode; a pin terminal for receiving a test address TAD which designates a memory cell to be accessed in the DRAM core MCR in a test mode; a pin terminal for receiving write data (test input data) TDin at the time of an operation test; and a pin terminal for receiving test output data TDout from the test interface circuit TIC at the time of an operation test.
Each of the test input data TDin supplied to the test interface circuit TIC and the test output data TDout outputted from the test interface circuit TIC is set to have a bit width of, for example, eight bits in a manner similar to a general DRAM.
The test interface circuit TIC includes a latch/command decoder
1
for performing data processes of taking in the test control signal TCMD, test address TAD, and test input data TDin supplied to the test pin terminal group TPG synchronously with the test clock signal TCLK, decoding the test control signal to an internal command (operation mode signal) so as to be issued to the DRAM core MCR, expanding the 8-bit test input data TDin to write data of 256 bits, and the like.
The test interface circuit TIC further includes: a mode register
2
for storing information such as column latency of the DRAM core MCR; a CA shifter
3
for generating a read data selection signal RD_S by shifting a read selection signal supplied from the latch/command decoder
1
in accordance with the column latency information stored in the mode register
2
; and a read data selection circuit
4
for performing 256:8 test output data selection of selecting 8-bit data from 256-bit data read from the DRAM core MCR in accordance with the read data selection signal RD_S from the CA shifter
3
.
As test peripheral circuits, provided are: a selector
5
for selectively coupling the DRAM core MCR to one of the large-scale logic device and the test interface circuit TIC in response to a test mode instruction signal TE; a gate circuit
6
which receives a clock signal CLK supplied from, for example, the large-scale logic device in an ordinary operation mode and the test clock TCLK supplied at the time of the operation test and supplies an operation clock signal DCLK to the DRA
Arimoto Kazutami
Shimano Hiroki
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