Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-06-22
2002-04-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S063000, C365S096000, C257S209000, C257S529000
Reexamination Certificate
active
06373772
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a fuse and a fuse latch circuit, and more particularly to a layout of these fuses and fuse latch circuits.
FIG. 1
is a layout of conventional fuses and fuse latch circuits.
FIG. 1
shows an example of a fuse and a fuse latch circuit, used for a redundancy circuit in semiconductor memory.
As shown in
FIG. 1
, the conventional fuses (FUSE) and fuse latch circuits (FUSE LAT.), which correspond one to one to the fuses, are disposed in a fuse area
101
and a fuse latch circuit area
102
, which are adjacent to each other on a chip.
Basic patterns
103
and
104
are available to dispose fuses and fuse latch circuits, respectively. In the fuse area
101
and fuse latch circuit area
102
, these basic patterns
103
and
104
are repeated a predetermined number of times to lay out a predetermined number of fuses and fuse latch circuits on a chip.
A repetition pitch P
2
between the basic patterns
104
of the conventional fuse latch circuits is equal to a repeating pitch P
1
between the basic patterns
103
of the conventional fuses. This is because equalizing the repetition pitches P
2
and P
1
helps connect the fuses with the fuse latch circuits, corresponding to the fuses.
In the fuse latch area
102
, some basic patterns
104
can be repeatedly used for each fuse latch circuit; others are not. For example, for the fuse latch circuits used for a redundancy circuit, which are in
FIG. 1
, repeatable basic patterns
104
are common to a plurality of addresses, and unrepeatable patterns are for local address signal lines
105
. The local address signal lines
105
connect global address signal lines disposed, for example, in the direction of repeated basic patterns
104
with the fuse latch circuits.
Different addresses could be entered for different fuse latch circuits. Because of this, a hierarchy in which a pattern of local address signal lines
105
is laid out differs from a hierarchy in which a pattern common to a plurality of addresses. Here the term “hierarchy” does not mean a “physically upper or lower level.” For example, in semiconductor memory, a plurality of the same layouts are provided. Thus in a layout block (cell), another layout block is frequently disposed. Such a structure is called a “hierarchy” in a layout.
Each local address signal line
105
differs from a basic pattern
104
of fuse latch circuits in terms of hierarchy but is laid out where the basic pattern
104
is disposed.
However, such a layout increases the number of local address signal lines
105
. As a result, the total parasitic capacitance of address signal lines, including global address lines, increases, thus markedly delaying address signal transmission.
To solve this problem, a semiconductor memory device is adapted so that the number of local address signal lines
105
is reduced by disposing a plurality of fuse latch circuits corresponding to the same address in a group and making the local address signal lines
105
common to the plurality of fuse latch circuits to reduce the total parasitic capacitance of address signal lines, as shown in
FIG. 2
(Jpn. Pat. Appln. KOKAI Publication No. 11-135754).
However, at any rate, a local address signal line
105
differs from a basic pattern
104
of fuse latch circuits in terms of hierarchy but is laid out where the basic pattern
104
is disposed. This requires that the basic pattern
104
of fuse latch circuits is provided with a space (or an area)
106
in which local address signal lines are disposed. Because wiring in the same wiring layer as the local address signal lines
105
cannot be installed in the space, layout is restricted.
Such a restriction limits the flexibility of layout and prevents area in which fuse latch circuits are disposed from being reduced, and moreover, increases unnecessary area.
The basic pattern
104
of fuse latch circuits is repeated in a conventional fuse latch area
102
so that the patterns are close to each other, patterns which do not necessarily need to be repeated at the pitch P
2
are repeated.
Such patterns are contacts to a semiconductor substrate or a well.
Also because patterns which do not necessarily need to be repeated at the pitch P
2
are repeated than necessary, fuse latch circuit area reduction is prevented, or fuse latch circuit area even increases.
BRIEF SUMMARY OF THE INVENTION
It is a main object of the present invention, made in the light of the foregoing, to provide a semiconductor integrated circuit device which allows restrictions on fuse latch circuit layout to be removed and fuse latch circuit area to be minimized.
It is another object of the present invention to provide a semiconductor integrated circuit device which allows blow errors to be reduced even if the pitch of repetition of a basic pattern for a fuse is reduced to below the minimum positioning repetition pitch of a blow machine.
To attain the main object, a first semiconductor integrated circuit device according to the present invention comprises a fuse area; a plurality of first layout sections disposed in the fuse area at a first repetition pitch, in each of which sections a fuse is laid out; a fuse latch circuit area; a plurality of second layout sections disposed in the fuse latch circuit area at a second repetition pitch smaller than the first repetition pitch, in each of which sections a fuse latch circuit corresponding to each of the fuses is laid out; and at least one third layout section disposed in a space created by the difference between the first and second repetition pitches, where at least one pattern which is unrepeatable in each of the plurality of second layout sections and at least one pattern which does not need to be repeated in each of the plurality of second layout sections is laid out.
In the first semiconductor integrated circuit device, at least one of a pattern which is unrepeatable in each second layout section and a pattern which does not need to be repeated in each second layout section is laid out in a third layout section. This arrangement removes, restrictions on layout in second layout sections or prevents patterns which do not need to be repeated from being repeated than necessary, thus allowing fuse latch circuit area to be minimized.
To attain the main object, a second semiconductor integrated circuit device according to the present invention comprises a fuse area; a plurality of first layout sections disposed in the fuse area at a first repetition pitch, in each of which sections a fuse is laid out; a fuse latch circuit area; and at least one second layout section disposed in the fuse latch circuit area, in which section n fuse latch circuits corresponding to the n fuses are laid out (n meets the inequality n>1).
In the second semiconductor integrated circuit device, fuse latch circuits which correspond to n fuses are disposed in second layout section. Because of this, in the second layout section, as many layout patterns as necessary such as patterns which cannot be repeated or do not need to be repeated for each fuse latch circuit have only to be provided for the fuse latch circuits corresponding to the n fuses. Thus compared with a case where the above-described patterns are formed for each fuse latch circuit, restrictions on layout in the second layout sections are reduced, thus allowing fuse latch circuit area to be minimized.
To attain the other object, a third semiconductor integrated circuit device according to the present invention comprises a fuse area and a plurality of layout sections disposed in the fuse area, in which sections a fuse is laid out, wherein the plurality of layout sections are disposed at irregular pitches in the fuse area.
In the third semiconductor integrated circuit device, the first layout sections in which fuses are laid out are laid out at irregular repetition pitches. For example, doing so allows blow errors to be reduced if regular pitches shift from the minimum positioning repetition pitch of a fuse blow machine.
Additional objects and advantages of the invention will be set forth in
Kato Daisuke
Watanabe Yohji
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nguyen Tan T.
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