Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-06-26
2004-12-14
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S050000, C257SE21524
Reexamination Certificate
active
06831294
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device (hereinafter also called simply a “semiconductor integrated circuit”), and specifically to a semiconductor integrated circuit (hereinafter also called simply a “flip-chip type semiconductor integrated circuit”) in which protruding electrodes (hereinafter also called simply “bump electrodes”) such as solder bumps or the like used for circuit substrate mounting are formed on a semiconductor substrate. The present invention relates particularly to a structure of a flip-chip type semiconductor integrated circuit in which attention has been directed toward a probe test, and a manufacturing method thereof, and relates to, for example, a technology effective for application to a system LSI or the like mixed with a memory and a logical circuit or the like, and a manufacturing method thereof.
Further, the present invention relates to a semiconductor integrated circuit wherein protruding electrodes (hereinafter also called simply “bump electrodes”) such as solder bumps or the like for circuit substrate implementation are formed on a semiconductor substrate and program elements each of which permanently or irreversibly changes the function of a predetermined portion of the semiconductor integrated circuit, are installed thereon.
BACKGROUND ART
The following references are known as examples of references each of which has described a semiconductor integrated circuit having bump electrodes used for circuit substrate implementation.
(a) Unexamined Patent Publication Hei 5(1993)-218042, (b) Unexamined Patent Publication Hei 8(1996)-250498 and (c) U.S. Pat. No. 5,547,740 respectively show one basic form of a flip-chip type semiconductor integrated circuit mentioned in the present specification. Namely, the flip-chip type semiconductor integrated circuit is configured as follows. For example, relocation wirings are routed from bonding pads of its chip, bump electrodes respectively connected to the relocation wirings are laid out on the surface of the chip in array form (in area array form), and the bump electrodes arranged in area array form are exposed from a surface protection film. It is thus possible to enlarge the interval between the bump electrodes, facilitate substrate mounting that the bump electrodes are respectively connected to wirings for a printed circuit board and utilize a low-cost printed circuit board in which wiring intervals are wide.
In the flip-chip type semiconductor integrated circuit, the bump electrodes are terminals capable of being directly mounted or implemented on a circuit substrate and are equivalent to external connecting terminals such as lead pins or the like for a package. After the bump electrodes are formed and wafer processes are all completed, only the bump electrodes are exposed and the bonding pads are finally covered with an insulating film or a protection film.
The present inventors have compared the number of the bonding pads in the semiconductor chip with the number of the external terminals (bump electrodes) typified by the lead pins for the package. According to the comparison, bonding pads used only for probe inspection and bonding pads connected to power terminals or the like by a technique for a bonding option are not assigned external terminals dedicated therefor. Thus, when the flip-chip type semiconductor integrated circuit is substituted for the semiconductor integrated circuit, a wafer probe test can be performed through the use of all bonding pads if it is antecedent to the formation of the relocation wirings and bump electrodes. However, it has been found out by the present inventors that there is a fear that when a probe is brought into direct contact with each bonding pad, the bonding pad is endamaged and a failure in connection to each relocation wiring occurs.
Techniques for probe testing are not described in the References (a) through (c) at all. The technology of forming under bump metals or metallurgies on bonding pads after having been subjected to probe testing or inspection, has been described in, for example, (d) Michael J. Varnau: “Impact of Wafer Probe Damage on Flip Chip Yields and Reliability”, International Electronics and Manufacturing Technology Symposium (Oct. 23-24, 1996) as a reference in which the relation to the probe inspection has been described. As to the reference described in the paragraph (d), however, there is a possibility that when a probe is applied to one of bonding pads antecedent to a relocation wiring process, the surface of the bonding pad will damage and the reliability of connection to a relocation wiring layer will be degraded, as discussed above by the present inventors. A limitation is imposed on the selection of a relocation wiring material.
Further, the following References are known as to the probe tests performed in the flip-chip type semiconductor integrated circuit.
(e) The technology of applying a probe to each under bump metal or metallurgy (UBM) antecedent to the formation of bump electrodes to perform a probe test has been described in U.S. Pat. No. 5,597,737.
(f) A configuration wherein testing pads are provided so as to adjoin under bump metallurgies and be connected thereto, has been shown in Unexamined Patent Publication No. Hei 8(1996)-64633. The testing pads are respectively provided at the sides of bump electrodes.
(g) Unexamined Patent Publication No. Hei 8(1996)-340029 shows a description related to the invention wherein portions directly above bonding pads at which relocation wiring layers are formed, are exposed and testing pads for probe inspection are formed at their exposed portions.
(h) Unexamined Patent Publication No. Hei 8(1996)-29451 shows a description related to the invention wherein each of pads for probe testing is formed by a relocation wiring layer in the neighborhood of each bonding pad.
The present inventors could obtain the following results by further discussing the technologies described in the References referred to above.
It has been revealed by the present inventors that the technology described in the paragraph (e) also has the possibility that each under solder bump metallurgy will be endamaged at a probe tip in a manner similar to the technology described in the paragraph (d), and has led to degradation in wettability relative to solder and degradation in reliability of connections to each solder bump electrode due to the damage of a barrier metal used for the prevention of solder diffusion.
Further, the under bump metallurgies are placed in area array form in a manner similar to the bump electrodes in the technology described in the paragraph (e). In the technology described in the paragraph (f), the testing pads are also laid out in area array form together with the bump electrodes. Therefore, it has been revealed by the present inventors that each of the technologies described in the References (e) and (f) has a new problem in that it is difficult to apply a normally-used cantilever type probe to under bump metallurgies or testing pads arranged in a multiple row, and terminal-dedicated expensive probes disposed in area array form are additionally required.
It has been found out by the present inventors that the Reference described in the paragraph (g) has a problem in that when the size of each bonding pad and the interval between the bonding pads become narrow with high integration of a semiconductor device, the sizes of the testing pads and the interval therebetween become also narrow, and the positioning of each probe and reliable contact thereof fall into difficulties.
It has been revealed by the present inventors that the technology described in the paragraph (h) has the fear that since the area of each testing pad is added to its corresponding relocation wiring layer, the capacitance of a wiring increases and the electrical characteristic of a semiconductor integrated circuit is degraded.
It has been revealed by the present inventors that each of the References described in the paragraphs (f) through (h) is accompanied by a problem that since the tes
Kitsukawa Gorou
Miyamoto Toshio
Nishimura Asao
Syukuri Syouji
Coleman W. David
Mattingly Stanger & Malur, P.C.
Renesas Technology Corp.
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