Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-10-26
2003-02-11
Ho, Hoai (Department: 2811)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189110, C365S226000, C365S230030
Reexamination Certificate
active
06519191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a layout of an internal voltage generating circuit for generating an internal voltage utilized in the semiconductor integrated circuit device. More particularly, the invention relates to the structure of the internal voltage generating circuit suitable to a power supply for a Dynamic Random Access Memory (DRAM) included in a logic-merged memory, in which a semiconductor memory such as a DRAM and a logic are integrated on a single chip.
2. Description of the Background Art
FIG. 47
schematically shows a chip layout of a conventional semiconductor integrated circuit device. In
FIG. 47
, a semiconductor integrated circuit device
900
includes pads
902
arranged on a periphery of a chip, a DRAM macro
903
, and first, second and third merged circuits
905
,
907
and
909
arranged in a region surrounded by pads
902
. Each of these first to third merged circuits
905
,
907
and
909
is formed of, e.g., a logic performing predetermined processing, a Static Random Access Memory (SRAM), a flash memory or the like.
In semiconductor integrated circuit device
900
, a hierarchical design method is used. DRAM macro
903
, and first to third merged circuits
905
,
907
and
909
are designed as macros, respectively, and these macros are arranged on the chip.
DRAM macro
903
has a storage capacity of 32 Mbits, and the input/output data bits are 256 bits (256 I/Os).
With advance of the semiconductor technology, it is now possible to form a logic and a DRAM on a single chip. The DRAM and the logic formed on the same ship are connected merely via internal interconnection lines of small load. Therefore, a data transfer rate between the logic and the DRAM can be made high. Further, the internal interconnection pitch is not affected by a pitch of pads
902
, and the internal data bus can have a large bit width so that the band width of data transfer can be increased.
In semiconductor integrated circuit device
900
shown, e.g., in
FIG. 47
referred to as a “logic-merged DRAM” hereinafter, the contents of processing to be performed by a logic (e.g., first merged circuit
905
) changes depending on the application, an therefore the memory capacity required by this logic (e.g., first merged circuit
905
) changes. Accordingly, it is necessary to develop a core chip serving as a base, and memories (DRAM macros
903
) having storage capacities according to the individual applications must be developed based on the core chip within a short time period.
For implementing the memory arrays having different storage capacities within a short time period, the following approach is most effective: the layouts of the repetition circuits such as the memory cells and associated direct control circuit (array circuit), in which the circuits of the same configuration are repeatedly arranged, such as sense amplifier and address decode circuit, are individually cellulated in advance, and respective cells are arranged in accordance with a practically required storage capacity. Particularly, in the recent years, a CAD (Computer Aided Design) tool such as a module generator, which can automatically perform such arrangement, has been developed. Further, as for other control circuits in the DRAM macro, it is now possible to perform automatic layout and interconnection in accordance with a floor plan similarly to usual logics, so that the layout period can be shortened with less persons.
In DRAMs, internal voltages at various voltage levels are used.
FIG. 48
schematically shows a structure of a circuit generating an internal voltage included in DRAM macro
903
. In
FIG. 48
, internal voltage generating circuitry (power supply circuit) for the DRAM includes an internal power supply circuit
912
for producing an array power supply voltage VCCS from external power supply voltage VEX, an intermediate voltage generating circuit
914
receiving array power supply voltage VCCS to produce intermediate voltages VCP and VBL, and a pump voltage generating circuit
916
receiving external power supply voltage VEX from external power supply node
910
, for performing, e.g., a charge pump operation to produce a boosted voltage VPP and a negative substrate bias voltage VBB.
FIG. 49
shows a structure of an array of the DRAM. In
FIG. 49
, the memory array of the DRAM includes memory cells MC arranged in rows and columns, word lines WL arranged for the respective memory cell rows. Bit line pairs BL and /BL are arranged corresponding to the columns of memory cells MC, respectively. Memory cell MC includes a capacitor MQ for storing information, and an access transistor MT for connecting memory capacitor MQ to bit line BL (or /BL) in response to the potential on word line WL.
Bit line pair BL and /BL is provided with a bit line equalize circuit BEQ for precharging bit lines BL and /BL to intermediate voltage VBL level when made active, and a sense amplifier circuit SA for transmitting array power supply voltage VCCS onto bit line at a higher potential of paired bit lines BL and /BL when made active.
Word line WL is driven to boosted potential VPP level when selected. Substrate bias voltage VBB is applied to a back gate of access transistor MT. Intermediate voltage VCP is applied to one electrode (cell plate electrode) of memory cell capacitor MQ.
As shown in
FIGS. 48 and 49
, a power supply interconnection line of a large width for supplying an array power supply voltage as well as voltage transmission lines of relatively large widths for transmitting internal voltages VCP, VBL, VPP and VBB are disposed in a portion for generating internal voltages for the DRAM. In the memory array of DRAM, signal lines are set to various voltage levels.
Internal power supply circuit
912
, intermediate voltage generating circuit
914
and pump voltage generating circuit
916
produce voltages at required levels in accordance with a reference voltage or a reference current. These reference voltage and reference current are always consumed after power-on. For reducing the power consumption, the circuit producing the reference voltage as well as the circuits supplied with the reference voltage are configured to consume a sufficiently small current, and the current drive capabilities of these reference current supply circuit and reference voltage generating circuit are sufficiently reduced. Therefore, the signal lines transmitting the reference current and the reference voltage are driven by small driving capabilities, and therefore are susceptible to noises applied from other signal lines or the substrate.
For verifying the layout of the above internal voltage generating circuitry, EDA tools such as layout reference check (DRC: Design Rule Check) usually performed and match verification (LVS: Layout Versus Schematic) between schema (logical description of layout) and layout are employed, but stable operations are insufficiently ensured in many cases. Under present circumstances, therefore, it is required to perform, by a skilled engineer, a minute and precise layout work with sufficient measures taken against noises and sufficient margins. In such a power supply circuit (internal voltage generating circuitry) layout, it is necessary to review or reconsider the power supply interconnections as well as the layout for achieving a sufficient immunity against noises and an optimum current supply capability when a floor plan changes in accordance with a storage capacity of the memory. This complicates the design, and impedes reduction in layout period.
For flexible conformance with various storage capacities, a method of utilizing a module structure is proposed by T. Watanabe et al., in “A Modular Architecture for a 6.4-Gbyte/s, 8-Mb DRAM-Integrated Media Chip”, IEEE Journal of Solid State circuits, Vol. 32, No. 5, pp. 635-641, May 1997. Watanabe et al. handle an expandable bank, a main amplifier for data reading and a voltage generator as one macro. According to the structure of Watanabe et al., the vo
Ho Hoai
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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