Semiconductor integrated circuit device having an ESD...

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C326S083000, C326S089000, C327S387000, C327S389000, C327S405000

Reexamination Certificate

active

07123054

ABSTRACT:
A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive
on-conductive state of the current path of the switching element.

REFERENCES:
patent: 5475333 (1995-12-01), Kumagai
patent: 5596295 (1997-01-01), Ueno et al.
patent: 5612582 (1997-03-01), Shichi et al.
patent: 6249414 (2001-06-01), Lee et al.
patent: 6356138 (2002-03-01), Ohshima
patent: 6433979 (2002-08-01), Yu
patent: 7-240510 (1995-09-01), None
patent: 2001-308282 (2001-02-01), None
patent: 02/075891 (2002-09-01), None
“GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Process” by C. Russ, M. Mergens, K.Verhaege, J. Armer, P. Jozwiak, G. Kolluri, L. Avery Published in 2001.
Notification of Reasons for Rejection mailed on Oct. 3, 2005 in connection with the related Japanese Patent Application No. 2003-209073. English translation of the Office Action is enclosed.
Russ, et al., “GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Proceses,” EOS/ESD Symposium, 2001. Sep. 9-13, 2001.

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