Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2002-07-09
2004-04-06
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S552000, C714S726000, C714S729000, C714S730000
Reexamination Certificate
active
06717235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device with logic circuits built-in, specifically to a design for testability for integrated circuits.
2. Description of Related Art
Recently, the scan testing technique has been the trend in the design for testability for logic circuits. Since the test pattern can easily be generated with the use of the substantial automatic test pattern generation tool (ATPG), it is no exaggeration to say that the scan testing technique becomes general in the field of the short-delivery semiconductor circuit device (hereunder, referred to as LSI). However, to leave the generation of test patterns to the ATPG will not always produce good and excellent test patterns.
Here, the ATPG means a software to automatically generate test patterns that enable detection of estimated faults in the nodes of a circuit from the judgment of only the circuit structure, based on the circuit information (in other words, the test patterns that allow controls and observations of 1-to-0 transitions from external terminals). In the present circumstances, it is general to premise that there is one or zero fixed fault in the whole circuit as a fault model (referred to as single stuck-at fault; Stuck-At-0 or Stuck-At-1). However, it is an experimental knowledge that even the test pattern generated by this model detects multiple faults or non-stuck-at faults at a considerable degree. Here, the test pattern generated by this model is generated regardless of the functional meaning of the circuit, and it means a defect check pattern, in distinction from a functional test pattern used for the functional verification of the design.
Next, there is a fault coverage that can be quoted as an indicator to quantitatively represent the quality of a test pattern. This coverage is to represent the degree how far the ATPG test pattern detects the faults estimated in the target circuit. In practice, the test pattern of the high fault coverage by the ATPG requires a considerable time, on the contrary to the strong request for the short delivery time, and there frequently occur situations that lead to reduction of the test pattern within a realistic range, or abandonment of the fault detection in a specific area. With regard to the fault detection in a specific area, a simulation pattern used for a sign-off condition with a customer, or a means to compensate to the best by a newly created pattern is often applied.
On the other hand, a means for testing plural LSIs simultaneously on an inexpensive tester will be often introduced on a mass production for the purpose of further cost reduction. However, an inexpensive tester usually involves the restriction on the number of test pins, which leads to the restriction of the simultaneously measurable number of the LSIs.
Referring to
FIGS. 8A
,
8
B and
FIGS. 9A
,
9
B, this situation will be described. FIG.
8
A and
FIG. 9A
illustrate the construction of an LSI test system adapted to a conventional tester, and the tester head has 280 pins spec. FIG.
8
B and FIG.
9
B illustrate the connection of the LSI tester. In the drawings,
1001
denotes the tester head,
102
a
and
102
b
denote 200-pin LSIs,
103
a
and
103
b
denote 100-pin LSIs, and
105
denotes an LSI interface.
In
FIG. 8
, simultaneous measurements can be made only within the number of the LSIs that satisfies the relationship: the LSI interface
105
of the tester head
1001
≧(the pin number of the LSI)×n (n: the number of the LSIs). Consequently, the LSIs
102
a
and
102
b
having 200 pins cannot be measured simultaneously, on the tester having the test pin restriction of 280 pins. This is a very exaggerated case. In case of an LSI having 110 input pins and 90 output pins, for example, two of the LSIs can be measured simultaneously. That is, the input pins should be shared by both of the LSIs. However, the extent to which the simultaneous measurement becomes possible depends upon the rate of the number of the input pins against that of the output pins, but a general standard for this rate is not provided.
In such a case, considering the reduction of the fault coverage within a permissible range, it is conceivable to reduce the pin number of the LSIs that the tester can access to thereby realize the simultaneous measurement. For example, as to the LSI in which the fulfillment of the fault coverage 98% is premised on the condition that all the pins of the 200-pin LSI are accessed, the alteration of the above premise into 90% is presumed approved. And, assuming that the fault coverage 90% can be achieved with the access to 100 pins, the foregoing tester will be able to measure the two 100-pin LSIs
103
a
and
103
b
simultaneously (see FIG.
9
). In this manner, since the scale of the tester head
1001
is generally small in an inexpensive tester, the arrangement is made to reduce the number of the pins requiring the access for testing within a range that the lowering in the fault coverage is permitted, whereby the simultaneous measurement is achieved by treating the number of the LSI pins apparently fewer. Here, the 100-pin LSI means one that, although it is originally the 200-pin LSI, is treated as a 100-pin LSI at the sacrifice of the capability of controls and observations.
In such a case, the access routes to the pads and internal circuits of the LSI are apt to become major areas where the fault detection is to be abandoned.
FIGS. 10A and 10B
illustrate a concrete example of the above. In the drawing,
201
denotes a pad,
301
and
302
denote internal circuits such as combination circuits, and
203
denotes a scan shift register composed of plural SFFs. Smeared parts in
FIG. 10B
, which do not exist in the combination circuits in
FIG. 10A
, represent the areas where the fault detection is to be abandoned. In this manner, there is an inconvenience that the restriction of the accessible pin number will lead to an insufficient detection of the faults, with regard to the circuit areas to which unusable pins have been connected directly or indirectly.
Next, the conventional test operation of an LSI will be described with reference to the accompanying drawings.
FIG.
11
and
FIG. 12
are the block diagram and the circuit diagram of a conventional semiconductor integrated circuit device, respectively, and
FIG. 12
represents the minimum circuit diagram to simplify the explanation. In the drawings, reference numeral
3
designates a combination circuit,
11
designates an input (DI) pad,
12
designates an output (DO) pad, and these pads are in charge of the interface between the LSI and the outside. Reference numeral
21
designates a scan input (SI) pad that enters a scan pattern, and
22
designates a scan output (SO) pad that delivers a scan out, that is, outputs a test result. Further, reference numeral
23
designates a scan mode (SM) pad that is used for the activation/deactivation control of a testing shift register (scan path), and
24
designates a testing clock (CLK) pad. Still further, reference numeral
31
designates a scan flip-flop (SFF), and consecutive SFFs constitute a testing shift register (scan path). Reference numerals
55
and
56
each designate an inverter, and
101
designates a circuit area including the combination circuit
3
and SFFs
31
.
Next, the operation will be described by each step.
(1) The ATPG recognizes the testing clock (CLK), scan mode (SM), scan input (SI), scan output (SO), input pad (input pin), and output pad (output pin), and generates the test pattern.
(2) The ATPG treats the SM as, for example, ‘L’ level, and activates the scan path. At that moment, the input d to the SFF
31
(the input from the combination circuit during the normal operation) is invalidated, and the terminal si to each SFF is made valid.
(3) The pattern that the ATPG generates from the SI pad
21
propagates synchronously with the CLK on the scan path toward the SO pad
22
.
(4) After completing the pattern setting to the SFF
31
located closest to the SO pad
22
, the A
Burns Doane Swecker & Mathis L.L.P.
Huynh Yennhu B
Jr. Carl Whitehead
Renesas Technology Corp.
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