Semiconductor integrated circuit device having a plurality of in

Details Semiconductor integrated circuit device having a plurality of in Semiconductor integrated circuit device having a plurality of in

1992-09-17

1994-08-23

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With contact or metallization configuration to reduce...

257500, 257692, 361767, 361780, H01L 2702

Patent

active

053410181

ABSTRACT:
Disclosed hereby is a technique to compensate for variations of the logical thresholds of the plurality of input initial stage circuits of a semiconductor integrated circuit due to the parasitic resistances of wiring layers (the power supply wiring layer and the ground wiring layer) for the supply of a fixed potential.
The dimensions of the transistors constituting the input initial stage circuits, for instance the channel widths of the N-channel MOSFET's of CMOS inverters, are enlarged to compensate for an increase in the logical thresholds due to the parasitic resistances of the ground wiring layer. The unevenness of logical thresholds of the plurality of input initial stage circuits due to their respective positions in the semiconductor chip can be thereby reduced.

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patent: 5063429 (1991-11-01), Crafts
patent: 5121036 (1992-06-01), Fuji

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