Semiconductor integrated circuit device having a compact arrange

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257205, 257659, 257903, H01L 2976, H01L 2710, H01L 23552, H01L 2711

Patent

active

053961005

ABSTRACT:
Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

REFERENCES:
patent: 4597805 (1986-07-01), Mohan Rao
patent: 4709351 (1987-11-01), Kajigaya
patent: 5132771 (1992-07-01), Yamanaka et al.
patent: 5148255 (1992-09-01), Nakazato et al.
patent: 5160995 (1992-11-01), Wada et al.
IEDM 88, "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell having excellent Soft error immunity", pp. 48-51, by Yamanaka et al.

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