Semiconductor integrated circuit device for scan testing

Details Semiconductor integrated circuit device for scan testing Semiconductor integrated circuit device for scan testing

2008-10-23

2011-12-27

Auve, Glenn A (Department: 2111)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C714S726000, C714S729000

Reexamination Certificate

active

08086889

ABSTRACT:
A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.

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patent: 2003-240822 (2003-08-01), None
patent: 2005-024359 (2005-01-01), None

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