Semiconductor integrated circuit device fabrication method

Details Semiconductor integrated circuit device fabrication method Semiconductor integrated circuit device fabrication method

2006-08-09

2011-11-01

Chea, Thorl (Department: 1795)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S005000, C430S024000, C430S317000, C430S329000, C430S396000, C355S035000, C355S052000, C355S053000, C355S077000, C438S975000, C438S976000, C438S780000

Reexamination Certificate

active

08048614

ABSTRACT:
A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.

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M. Hoga et al, ‘Photo the mask gijutu no hanashi’, Kougyou Chousakai KK, pp. 235-240, Aug. 20, 1996.

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