Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-27
2004-04-20
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06725440
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate and an exposure method employed for fabricating the same.
In fabrication of semiconductor integrated circuit devices, a reduction projection aligner employed in a step and repeat drawing method (hereinafter referred to as an optical stepper) is widely used.
Semiconductor integrated circuit technology has been recently remarkably developed, and there has been a tendency for the minimum design rule to be reduced by approximately 70% and the chip area to be substantially doubled approximately every three years. In order to cope with the reduction and the increase of the chip area, an optical stepper has been variously developed not only to have larger numerical aperture (NA) and use exposing light of a shorter wavelength for improving resolution but also to have a larger area of an exposure region (field). In the newest optical stepper, one field has the maximum area of approximately 22 mm□ on a material to be exposed.
Furthermore, in fabrication of a semiconductor integrated circuit device having a dimension larger than one field of an optical stepper, for example, the following method has been employed (as is disclosed in Japanese Laid-Open Patent Publication No. 63-258042): The principal plane of a rectangular (herein including square) substrate to be formed into a semiconductor chip is partitioned into a plurality of small rectangular regions, each of which is dealt with as one field for exposure. A pattern of a functional block is formed within each small region and functional blocks of the respective small regions are connected to one another through interconnects crossing boundaries between the small rectangular regions. In this method, an interconnect for connecting the functional blocks (hereinafter referred to as a global routing) is formed by stitching the patterns transferred in the small rectangular regions in the exposure. Therefore, a global routing is generally formed in an interconnect layer having such a large width that a stitching error caused in stitching the patterns is negligible.
FIG. 5
is an enlarged plane view of a part of a conventional semiconductor integrated circuit device fabricated by the aforementioned method.
As is shown in
FIG. 5
, the principal plane of a substrate
80
is partitioned into a plurality of two-dimensionally arranged rectangular regions
81
(surrounded with broken lines). In using an optical stepper, each rectangular region
81
is dealt with as one field for exposure.
Furthermore, as is shown in
FIG. 5
, a first device group
82
a
, a second device group
82
b
, a third device group
82
c
and a fourth device group
82
d
each having fine patterns are respectively disposed in adjacent four rectangular regions
81
, specifically, in a first rectangular region
81
a
, a second rectangular region
81
b
, a third rectangular region
81
c
and a fourth rectangular region
81
d
. Each of the device groups
82
a
through
82
d
includes at least one semiconductor device formed on the substrate. Also, each of interconnects
83
for connecting the device groups
82
a
through
82
d
to one another is disposed so as to cross a boundary between the rectangular regions
81
, namely, a field boundary indicated with the broken line.
Specifically, each interconnect
83
is formed by mutually stitching the patterns transferred in the rectangular regions
81
in the exposure, and hence, a stitching error can be caused in a portion positioned on the field boundary in the interconnect
83
. Therefore, an interconnect layer for each interconnect
83
should be formed as a pattern layer having a comparatively large design rule so as not to cause disconnection or short-circuit derived from the stitching error.
On the other hand, in accordance with recent rapid development in shrink of devices, an electron beam stepper using electron beam as an exposing energy source (electron projection lithography; hereinafter referred to as EPL), attaining higher resolution than an optical stepper, has been studied and developed.
In an electron lens used in the EPL, aberration is abruptly increased as the orbit of electrons is farther from the optical axis. Therefore, it is difficult for the electron lens to have a large field (of 20 mm□ or more) as that of an optical lens. Accordingly, the following method is to be employed in the EPL: The principal plane of a substrate to be exposed is partitioned into small regions (hereinafter referred to as sub-fields) each with an area of approximately 250 &mgr;m□ so as to transfer a pattern in each of the sub-fields. The patterns formed in the respective sub-fields are stitched to one another so as to form the pattern of the entire semiconductor chip.
The increase of the NA and the field of an optical stepper leads to increase of a lens diameter of an imaging optical system. As a result, the lens diameter has already increased to the limit of industrial fabrication. Therefore, it is difficult to further increase both the NA and the field. In addition, since a mask pattern has been also reduced in accordance with the reduction of a device, it is also difficult to keep dimensional accuracy in a mask pattern.
Accordingly, in an optical stepper, the reduction ratio is examined to be decreased to ×⅙ through ×{fraction (1/10)} from the current reduction ratio of ×¼ through ×⅕. On the contrary, when the reduction ratio is decreased, it is difficult to form a circuit pattern of an entire semiconductor chip in one mask. Therefore, also in employing an optical stepper, some exposure method is being developed in order to form a pattern of an entire semiconductor chip with the principal plane of a substrate with the semiconductor chip partitioned into several fields in each of which a pattern is transferred.
When patterns transferred in respective fields or sub-fields are stitched to one another by using an optical stepper or EPL, however, a stitching error is caused in a stitched portion between the patterns as described above. For example, when the EPL is used, each sub-field with an area of approximately 250 &mgr;m□ has a stitched portion and a stitching error is caused in each stitched portion.
FIGS. 6A through 6C
are diagrams of exemplified stitching errors caused in stitched portions between patterns in a conventional semiconductor integrated circuit device. In
FIGS. 6A through 6C
, reference numerals
91
a
and
91
b
(each surrounded with a broken line) denote adjacent exposure regions (each corresponding to one field in an optical stepper or one sub-field in the EPL), a reference numeral
92
denotes a pattern formed by stitching patterns respectively transferred in the exposure regions
91
a
and
91
b
, and a reference numeral
93
denotes a stitched portion of the pattern
92
.
When the exposure regions
91
a
and
91
b
are away from each other as is shown in
FIG. 6A
, the stitched portion
93
of the pattern
92
is locally narrowed.
When the exposure regions
91
a
and
91
b
partially overlap each other as is shown in
FIG. 6B
, the stitched portion
93
of the pattern
92
is locally widen.
Alternatively, when the exposure regions
91
a
and
91
b
are shifted from each other as is shown in
FIG. 6C
, the stitched portion
93
of the pattern
92
is bent.
In an actual semiconductor integrated circuit device, the local dimensional variation of the pattern as is shown in
FIGS. 6A and 6B
and the bend of the pattern as is shown in
FIG. 6C
are mixed so as to cause stitching errors, resulting in degrading the performance and the reliability of the device. For example, when a stitching error is caused in a gate electrode formed on an active region, there arises a problem of variation in the threshold voltage and the like. Alternatively, when a stitching error is caused in an interconnect layer, stress migration or electromigration is caused, resulting in largely degrading the
Bowers Brandon
Garbowski Leigh M.
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
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