Semiconductor integrated circuit device capable of ensuring...

Details Semiconductor integrated circuit device capable of ensuring... Semiconductor integrated circuit device capable of ensuring...

2001-02-08

2003-08-05

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S226000

Reexamination Certificate

active

06603685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of a semiconductor integrated circuit device and, more particularly, to a circuit configuration operating at a voltage higher than in other circuit portions in a semiconductor integrated circuit device.
2. Description of the Background Art
In a semiconductor integrated circuit device, for example, in a dynamic random access memory (DRAM) as a semiconductor memory device, generally an internal power supply circuit is mounted, for supplying an internal boosted potential by boosting an externally applied power supply voltage.
More specifically, in a word line potential driving circuit of a DRAM, the above described internally boosted potential is used to make gate potential of an access transistor in a memory cell sufficiently high to prevent voltage drop in the access transistor.
When a sense amplifier band is shared by two memory cell blocks adjacent thereto, a gate circuit for selectively coupling a sense amplifier to a bit line pair in either one of the memory cell blocks is generally formed by an N channel MOS transistor. It is necessary that a signal level controlling such a gate circuit is at a level higher than the “H” level potential which can be generated in the bit line pair, that is, the internally boosted potential described above, in order to prevent the voltage drop in the gate circuit.
At this time, the high voltage is applied to the transistor constituting the gate circuit and the access transistor of the memory cell which is the transistor on the side of receiving the high voltage, only when these are selected.
By contrast, the transistor included in the internal power supply circuit for generating the internally boosted potential is subjected to such a high voltage for a longer period, and such a transistor operates under the severest condition considering the necessity of securing reliability.
One of the causes decreasing reliability of such a transistor operating with high voltage applied thereto is a deterioration mode caused by “hot carriers” generated in a high electric field region near the drain of the transistor.
More specifically, when a transistor is miniaturized while keeping constant the power supply voltage, electric field strength increases near the drain. Therefore, electrons flowing from the source to the drain through the channel obtains high energy from the high electric field near the drain junction, and turn to a so called “hot electrons.” The hot electrons collide and are ionized near a drain end, generating electrons.holes. Though the electrons flow into the drain, part of the electrons are introduced and captured as a gate current in a gate oxide film and causes increase in threshold voltage or decrease in conductance as time passes.
Degradation of transistor characteristics caused by “hot carriers resulting from impact ionization” is said to be more likely in an N channel MOS transistor than a P channel MOS transistor. The reason for this may be the fact that electrons have higher ratio of impact ionization than holes, and that impurity profile of the drain is more steep, and hence electric field near the drain is high.
Accordingly, in a circuit for driving a high voltage such as described above, conventionally, a transistor having an electric field relaxing drain structure, for example, in order to maintain reliability of the N channel MOS transistor, a transistor having an electric field relaxing drain structure, for example, an N channel MOS transistor having an LDD (Lightly Doped Drain) structure has been sometimes used. Alternatively, a circuit configuration has been adopted in which an N channel MOS transistor having a prescribed gate potential applied thereto is interposed between a boosting node and a discharging N channel MOS transistor, so as to relax drain.source voltage.
Recently, in an LSI for image processing, for example, sometimes such a device is manufactured in that a DRAM and a logic circuit are mounted mixed on one chip.
In such a case, generally an MOS insulating film is made thin, for example, insulating film of an MOSFET is made thin (for example, insulating film thickness Tox=2 to 3 nm), in order to improve transistor performance of the logic circuit. Here, the MOS insulating film of the MOSFET in an area where the DRAM is formed is set thicker than in the logic circuit, and the insulating film thickness is Tox=6 to 7.5 nm, for example. Such a structure is referred to as a “Dual-Tox” method, as MOS insulating films of two different thicknesses are used in one LSI.
Here, up to the generation of the DRAM and the logic circuit having the minimum design dimension of 0.20 micron, an n
+
-polysilicon gate doped with n type impurity to a high concentration has been used as a gate electrode material both in P channel and N channel MOS transistors. Such a structure of the gate electrode material is referred to as “single gate method”.
In the single gate method, the N channel MOS transistor is a so called surface channel type MOS transistor, while the P channel MOS transistor is a buried channel type MOS transistor.
More specifically, in the single gate method, generally, an n type polycrystalline silicon (polysilicon) doped with a large amount of phosphorus (P) is used as the gate electrode material. Even in a polycide gate structure consisting of a stacked structure of a high melting point metal silicide and polycrystalline silicon, what is indirect contact with a gate oxide film is n type polysilicon.
When such gate electrode materials are used as the gate electrode of the N channel MOS transistor, the threshold voltage becomes lower, as there is a large difference in work function between a p type substrate and an n type polysilicon. Therefore, generally, in an N channel MOS transistor, impurities of the same conductivity as the substrate are ion-implanted to the channel region, so as to increase the threshold voltage.
When the n type polysilicon is used as the gate electrode of a P channel MOS transistor, the difference of work function between the n type substrate and the n type polysilicon is small, and therefore the threshold voltage increases in a negative direction. Therefore, when the absolute value of the threshold voltage is to be set at approximately the same value as that of the N channel MOS transistor, it becomes necessary that an impurity of an opposite conductivity to the substrate is ion-implanted to the channel region, so as to make smaller the absolute value of the threshold voltage.
As a result, in the P channel MOS transistor having the n type polysilicon as the gate electrode, a very shallow p-n junction is formed in the channel region, resulting in a buried channel type device. By contrast, the N channel MOS transistor having the n type polysilicon gate becomes a surface channel type device.
In the single gate method, the n type polysilicon is used as the gate electrode both in the N channel and P channel MOS transistors, and the threshold voltages of the N channel and P channel MOS transistors are adjusted to be approximately the same, by ion-implantation of boron to the channel region.
When such a structure is adopted, the position where the potential is the minimum is not at the Si—SiO
2
interface but in the substrate (well) in the P channel MOS transistor, and therefore, a buried channel is formed.
By contrast, from the generation where the circuit design rule attains 0.18 micron or smaller, a so called “dual gate method” comes to be adopted, in which the gate of the P channel MOS transistor is formed by p
+
-polysilicon gate and the gate of N channel MOS transistor is formed by n
+
-polysilicon.
In this case, both P and N channel MOS transistors are the surface channel type MOS transistors.
The reason why such an approach is taken is that the buried channel type device such as the conventional P channel MOS transistor is, though advantageous in that mobility increases as the carriers in the buried channel are less susceptible to the influence of surface scatteri

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