Semiconductor integrated circuit device capable of...

Details Semiconductor integrated circuit device capable of... Semiconductor integrated circuit device capable of...

2000-07-13

2004-03-30

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S701000

Reexamination Certificate

active

06715115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device in which parallel data output from an internal circuit (for example, a memory cell area) is converted into serial data, which is output to the outside of the device via a data output circuit.
2. Description of the Related Art
FIG. 1
is a circuit diagram of part of an example of a conventional DRAM (Dynamic Random Access Memory), which includes a data switch circuit
1
, an output buffer circuit
2
, and a pad
3
serving as an external connection terminal.
The data switch circuit
1
is controlled by a select signal SEL. At the time of a normal mode, read data RD read our from a memory cell area is selected, and is transmitted to an output buffer circuit
2
. At the time of a test mode, test data TD (which is, for example, internal information indicating the burst length) is selected output from a part other than the memory cell area, and is transmitted to the output buffer circuit
2
.
The output buffer circuit
2
is set to an output enable state by an output enable signal OEN, and outputs, as output data DOUT, the real data RD or test data TD output from the data switch circuit
1
to the pad
3
in synchronism with the timing of a falling edge of an output clock signal OCLK.
The output buffer circuit
2
includes an output transistor circuit
4
, which functions to output the output data DOUT to the pad
3
. The output transistor circuit
4
is made up of a PMOS (P-type Metal Oxide Semiconductor) transistor
5
serving as a pull-up element, and an NMOS (N-channel MOS) transistor
6
serving as a pull-down element.
An output transistor control circuit
7
, which supplies a pull-up signal PU and a pull-down signal PD to the gates of the PMOS and NMOS transistors
5
and
6
, respectively, so that the transistors
5
and
6
can be turned ON/OFF.
FIG. 2
is a circuit diagram of a configuration of the data switch circuit
1
, which is made up of NAND circuits
8
,
10
and
11
, and inverters
89
and
12
. The NAND circuit
8
performs a NAND operation on the select signal SEL and the test data TD. The inverter inverts the select signal SEL. The NAND circuit
10
performs a NAND operation on the output of the inverter
9
and the real data RD. The NAND circuit
11
performs a NAND operation o the outputs of the NAND circuits
8
and
10
. The inverter
12
inverts the output of the NAND circuit
11
, and outputs an output D
1
of the data switch circuit
1
.
The select signal SEL is at a low (L) level at the time of reading data in the normal mode, and is at a high (H) level at the time of the test mode. When the select signal is at L, the output of the NAND circuit
8
is at H, and the output of the inverter
9
is at H. Thus, the NAND circuit
10
functions as an inverter with respect to the real data RD, and the NAND circuit
11
functions as an inverter with respect to the output of the NAND circuit
10
. As a result, the real data RD is selected.
When the select signal SEL is at H, the output of the inverter
9
is at L, and the output of the NAND circuit
10
is at H. Thus, the NAND circuit
8
functions as an inverter with respect to the test data TD, and the NAND circuit
11
functions as an inverter with respect to the output of the NAND circuit
8
. As a result, the test data TD is selected.
FIG. 3
is a circuit diagram of the output transistor control circuit
7
, which includes a pull-up signal generating circuit
13
which generates the pull-up signal PU, and a pull-down signal generating circuit
14
which generates the pull-down signal PD.
The pull-up signal generating circuit
13
is made up of a NAND circuit
15
, an inverter
16
, a transfer gate circuit
17
, a PMOS transistor
18
, and an NMOS transistor
19
. The NAND circuit
15
performs a NAND operation on the output enable signal OEN and an output D
1
of the data switch circuit
1
. The inverter
16
inverts an output clock signal OCLK. The PMOS transistor
18
is turned ON/OFF by the output clock signal OCLK.
The NMOS transistor
19
is turned ON/OFF by the output of the inverter
16
.
Further, the pull-up signal generating circuit
13
includes a latch circuit
20
, and an inverter
23
. The latch circuit
20
is made up of inverters
21
and
22
, and latches the output of the NAND circuit
15
via the transfer gate circuit
17
. The inverter
23
inverts the output of the latch circuit
20
, and thus produces the pull-up signal PU.
The pull-down signal generating circuit
14
includes an inverter
24
, and a NOR circuit
25
. The inverter
24
inverts the output enable signal OEN. The NOR circuit
25
performs a NOR operation on the output of the inverter
24
and the output D
1
of the data switch circuit
1
.
Further, the pull-down signal generating circuit
14
includes an inverter
26
, a transfer gate circuit
27
, a PMOS transistor
28
, and an NMOS transistor
29
. The inverter
26
inverts the output clock signal OCLK. The PMOS transistor
28
is turned ON/OFF by the output clock signal OCLK. The NMOS transistor
29
is turned ON/OFF by the output of the inverter
26
.
Furthermore, the pull-down signal generating circuit
14
includes a latch circuit
30
, and an inverter
33
. The latch circuit
30
is made up of inverters
31
and
32
, and latches the output of the NOR circuit
25
via the transfer gate circuit
27
. The inverter
33
inverts the output of the latch circuit
30
, and thus produces the pull-down signal PD.
In the output transistor control circuit
7
thus configured, when the output enable signal OEN is at L, the output of the NAND circuit
15
is at H, and the output of the inverter
24
is at H, while the output of the NOR circuit
25
is at L.
In this case, when the output clock signal OCLK switches to L, the transfer gate circuits
17
and
27
are turned ON, so that the output of the latch circuit
20
is changed to L, and the pull-up signal PU is changed to H. The output of the latch circuit
30
is switched to H, and the pull-down signal PD is switched to L.
Thus, when the output clock signal OCLK switches to L in the state in which the output enable signal OEN is at L, the PMOS transistor
5
is turned OFF, and the NMOS transistor
6
is turned OFF. Consequently, the output buffer circuit
2
is changed to a high-impedance state.
In contrast, when the output enable signal OEN is at H, the NAND circuits
15
and NOR circuit
25
respectively function as inverters with respect to the output D
1
of the data switch circuit
1
.
In the above case, when the output D
1
of the data switch circuit
1
is H, the output of the NAND circuit
15
is at L, and the output of the NOR circuit
25
is at L. In these states, when the output clock signal OCLK switches to L, the transfer gate circuits
17
and
27
are turned ON. Thus, the output of the latch circuit
20
is switched to H, and the pull-up signal PU is switched to L. Further, the output of the latch circuit
30
is changed to H, and the pull-down signal PD is changed to L.
Thus, in the above case, the PMOS transistor
5
is turned ON, and the NMOS transistor
6
is OFF, while the output data DOUT is H. Thus, H which is the output D
1
of the data switch circuit
1
is output.
In contrast, when the output D
1
of the data switch circuit
1
is at L, the output of the NAND circuit
15
is at H, and the output of the NOR circuit
25
is at H. In these states, when the output clock signal OCLK switches to L, the transfer gate circuits
17
and
27
are turned ON. Thus, the output of the latch circuit
20
is switched to L, and the pull-up signal PU is switched to H. Further, the output of the latch circuit
30
is switched to L, and the pull-down signal PD is switched to H.
Thus, in the above case, the PMOS transistor
5
is turned OFF, and the NMOS transistor
6
is turned ON. The output data DOUT becomes L, and L which is the output D
1
of the data switch circuit
1
is output.
FIG. 4
is a waveform diagram illu

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