Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-10-18
2002-07-16
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S189011, C365S189070
Reexamination Certificate
active
06421286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a configuration of a semiconductor integrated circuit device integrated with a test circuit for performing a test thereon.
2. Description of the Background Art
Most of semiconductor memory devices have spare memory cells and in a case where a defective memory cell exists in a part of normal memory cells, the defective memory cell can be replaced with a spare memory cell to save a defective chip.
On the other hand, in a field where especially high speed data processing such as image processing is requested, a semiconductor memory device and a logic circuit for performing an operation on data stored in the semiconductor memory device have been integrated on the same chip. This is because, in this configuration, a circuit portion of a semiconductor memory device, for example a dynamic random access memory (the dynamic random access memory is hereinafter referred to as a DRAM and the circuit portion thereof is hereinafter referred to as a DRAM core) and a logic circuit are connected by a bus with a large width therebetween and both circuits are arranged adjacent to each other, thereby, enabling data supplying/receiving to be performed at high speed to realize higher speed operation.
FIG. 43
is a schematic block diagram for describing a test operation on a semiconductor integrated circuit device
8000
integrated with a DRAM core
8010
and a logic circuit
8020
.
Referring to
FIG. 43
, in a semiconductor integrated circuit device
8000
, there is further provided a tester interface section
8030
supplying/receiving of data between DRAM core
8010
and an external tester
8100
in order that a test for detecting a defective bit in a DRAM core is performed with external tester
8100
.
It is assumed that DRAM core
8010
and tester interface section
8030
integrated on semiconductor integrated circuit device
8000
are connected therebetween, for example, by an internal data bus having a 256 bit width. On the other hand, tester interface section
8030
and external tester
8100
are connected therebetween, for example, by an external data bus having an 8 bit width.
While in the interior of the chip, it is easy to increase a bus width of the internal data bus, that is the number of I/O, on the other hand a width of the external bus cannot be increased unlimitedly since the width relates to the number of pads and therefore, the number of pins for connecting semiconductor integrated circuit device
8000
with an external circuit.
Therefore, in a case where an analysis on a detective bit in DRAM core
8010
is performed with an external tester, it is required that the test is performed through an external data bus having a small width, having resulted in a problem of increase in a test time.
External tester
8100
sequentially performs writes of test data into memory cells in DRAM core
8010
through such a tester interface section
8030
. Furthermore, external tester
8100
sequentially performs reads of data from DRAM core
8000
through tester interface section
8030
to test the presence or absence of a defective bit based on a comparison result between read data and an expected value of the read data.
Therefore, in order to perform the test on DRAM core
8010
at high speed, external tester
8100
is also required to be adapted to an operating speed of DRAM core
8010
operating at high speed, thereby also having lead to a problem of increase in a cost of the external tester, itself. In external tester
8100
, a redundancy analysis is performed on what replacement process with combinations of redundant memory cell columns and redundant memory cell rows provided in DRAM core
8010
can realize saving on a detective bit that has been detected as described.
FIG. 44
is a schematic block diagram for describing a configuration of a semiconductor integrated circuit device
8200
integrated with a built-in self-test/redundancy saving analysis section
8230
in order to solve the problem in a test operation on DRAM core
8010
of semiconductor integrated circuit device
8000
in
FIG. 43. A
built-in self-test is hereinafter also abbreviated as “BIST”.
Semiconductor integrated circuit device
8200
includes: a DRAM core
8210
, a logic circuit
8220
for performing a logic operation on data stored in DRAM core
8210
; and built-in self-test/redundancy saving analysis section
8230
for detecting defective bits in DRAM core
8210
to analyze on what replacement process with combinations of redundant memory cell rows and redundant memory cell columns in DRAM core
8210
should be applied
A configuration of such a built-in self-test/redundancy saving analysis section
8230
is disclosed in, for example, Japanese Patent Laying-Open No. 2001-6387 or in a document, T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada and H. Hidaka, “A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs”, International Test Conference 2000 Proceedings, pp. 567-574.
Therefore, if built-in self-test/redundancy saving analysis section
8230
as shown in
FIG. 44
is integrated on semiconductor integrated circuit device
8200
, DRAM core
8210
and built-in self-test/redundancy saving analysis section
8230
can be connected therebetween by an internal data bus with a comparatively large bit width, for example a 256 bit I/O. Hence, Problems can be avoided of increase in test time and a cost required for an external tester device as described in FIG.
43
.
For example, in a case where plural DRAM cores with different memory capacities are integrated on one chip, however, there arises a problem to be further solved as described below:
FIG. 45
is a schematic diagram for describing a configuration of a semiconductor integrated circuit device
8400
integrated with plural DRAM cores on one chip.
A first DRAM core
8410
and a second DRAM core
8440
are integrated on semiconductor integrated circuit device
8400
. Provided to first DRAM core
8410
are: a logic circuit
8420
for supplying/receiving data with first DRAM core
8410
and performing a logic operation; and built-in self-test/redundancy saving analysis section
8430
for detecting a defective bit in first DRAM core
8410
and performing analysis for redundancy saving on first DRAM core
8410
.
On the other hand, provided to second DRAM core
8440
are: a logic circuit
8450
for supplying/receiving data with second DRAM core
8440
and performing a logic operation; and a built-in self-testing/redundancy saving analysis section
8460
for detecting a defective bit in second DRAM core
8440
and performing analysis for redundancy saving on second DRAM core
8440
.
Herein, it is assumed that a memory capacity of DRAM core
8440
is lager than that of DRAM core
8410
.
Therefore, it is assumed that, for example, while DRAM core
8410
and built-in self-test/redundancy saving analysis section
8430
are connected therebetween by a 256 bit internal data bus. DRAM core
8440
and built-in self-test/redundancy saving analysis section
8460
are connected therebetween by an internal data bus with a width of 2048 bits.
Furthermore, in general, DRAM core
8410
and DRAM core
8440
are different from each other in the number of redundant memory cell rows and the number of redundant memory cell columns.
Based on such differences in memory capacity and configuration of redundant memory cells, a necessity arises that provided to DRAM core
8410
and DRAM core
8440
are built-in self-test/redundancy saving analysis section
8430
and built-in self-test/redundancy saving analysis section
8460
, respectively, which are different from each other.
When, in such a manner, built-in self-test/redundancy saving analysis sections are provided to respective DRAM cores, there arise problems that an area penalty increases, thereby inviting increase in chip area.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit integrated with a test circuit capable of flexibly ad
Hidaka Hideto
Kawagoe Tomoya
Ohtani Jun
Ooishi Tsukasa
Elms Richard
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan T.
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