Semiconductor integrated circuit device and test method thereof

Details Semiconductor integrated circuit device and test method thereof Semiconductor integrated circuit device and test method thereof

2011-03-29

2011-03-29

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S723000, C257S737000

Reexamination Certificate

active

07915720

ABSTRACT:
The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices14and16, and a circuit board12which relays the respective semiconductor integrated circuit elements14and16, and at least a part of the circuit board12, e.g. test pads13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices14and16are electrically connected to the circuit board12.

REFERENCES:
patent: 5789930 (1998-08-01), Isaacs et al.
patent: 6493240 (2002-12-01), Broglia et al.
patent: 7129584 (2006-10-01), Lee
patent: 7129726 (2006-10-01), Tashiro et al.
patent: 7189593 (2007-03-01), Lee
patent: 2002/0063317 (2002-05-01), Hashimoto
patent: 2003/0042587 (2003-03-01), Lee
patent: 2003/0134450 (2003-07-01), Lee
patent: 2006/0249827 (2006-11-01), Fasano et al.
patent: 2006/0249828 (2006-11-01), Hong
patent: 10-242350 (1998-09-01), None
patent: 10-321760 (1998-12-01), None
patent: 2914308 (1999-06-01), None
patent: 11-191577 (1999-07-01), None
patent: 2000-88921 (2000-03-01), None
patent: 2004-241689 (2004-08-01), None
patent: 2005-353687 (2005-12-01), None
Toru Ishida “Advance Substrate and Packaging Technology”, 1998 IEMT/IMC Proceedings, pp. 18-24.
Japanese Office Action dated Jun. 22, 2010, issued in corresponding Japanese Patent Application No. 2006-001421.
Japanese Office Action dated Sep. 28, 2010, issued in corresponding Japanese Patent Application No. 2006-001421. (with partial English translation).

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device and test method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device and test method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and test method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2779243