Semiconductor integrated circuit device and standard cell...

Details Semiconductor integrated circuit device and standard cell... Semiconductor integrated circuit device and standard cell...

2002-10-29

2004-05-04

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06732344

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-331294, filed Oct. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a standard cell placement design method and more specifically to the placement of substrate contacts of a standard cell array.
2. Description of the Related Art
In designing standard cell-based LSIs, standard cells, which have previously been standard-designed, are placed through the use of CAD (computer aided design) or EDA (electronic design automation) tools. By suitably forming interconnect lines on the cell array to combine standard cells, any desired circuit can be constructed.
FIGS. 1A and 1B
are plan views of conventional standard cell placement patterns.
A standard cell
50
a
shown in
FIG. 1A
has a pattern
51
of active regions of a PMOS transistor, a pattern
52
of active regions of an NMOS transistor, a pattern
53
of a gate interconnection placed in common to the paired transistors (CMOS transistor pair), and patterns
54
of a pair of substrate contacts placed on the opposite sides of the gate interconnection pattern
53
. The active region pattern
51
of the PMOS transistor is formed on an N well region not shown. The active region pattern
52
of the NMOS transistor is formed on a P well region not shown. The paired substrate contact patterns
54
are placed to correspond to the N-well region and the P-well region, respectively.
A standard cell
50
b
shown in
FIG. 1B
has a pattern
51
of active regions of a PMOS transistor, a pattern
52
of active regions of an NMOS transistor, a pattern
53
of a gate interconnection placed in common to the paired transistors (CMOS transistor pair), and patterns
54
of a pair of substrate contacts each placed on one side of a corresponding one of the transistors. The active region pattern
51
of the PMOS transistor is formed on an N-well region not shown. The active region pattern
52
of the NMOS transistor is formed on a P-well region not shown. The paired substrate contact patterns
54
are placed to correspond to the N-well region and the P-well region, respectively.
FIG. 2
is a plan view of a portion of a cell array in which standard cells shown in
FIG. 1A
are placed.
That is, any desired circuit can be constructed by placing a number of standard cells
50
a
as shown in
FIG. 1A
to form an array and forming desired signal interconnections and power supply system on the array. For example, the use of a single standard cell
50
a
allows a CMOS inverter circuit to be formed. The use of two standard cells
50
a
can form a CMOS flip-flop circuit.
The conventional standard cell-based LSIs thus designed require a pair of substrate contacts
54
for each of standard cells that form a cell array. For this reason, the entire integrated circuit chip will have more substrate contacts than necessary.
The extra substrate contacts reduces the packing density of cells on a chip per unit area. In other words, the size of the standard cell array increases, resulting in an increase in chip size. In addition, since no interconnection can be placed on each substrate contact, the region where interconnections are to be placed on the chip will be reduced.
As described above, the conventional standard cell-based LSIs have problems that the size of the standard cell array increases, the chip size increases, and the interconnection region decreases.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a plurality of first standard cells that form a cell array, each of the first standard cells having no contact pattern; a second standard cell that forms the cell array in combination with the first standard cells, the second standard cell having first contact patterns; and second contact patterns placed within the cell array, the number of the second contact patterns being smaller than that of the first standard cells.
According to another aspect of the present invention, there is provided a standard cell placement design method comprising: providing a spare area where additional substrate contacts are to be placed in a cell array forming an area where a cell array is to be formed; placing first and second standard cells in that area in the cell array forming area where the additional substrate contacts are not to be placed, the first standard cells having no contact pattern and the second standard cells having first contact patterns; placing the second contact patterns in the spare area; and placing power supply interconnection patterns over the cell array forming area, the power supply interconnection patterns being connected to the first and second contact patterns.


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patent: 5369596 (1994-11-01), Tokumaru
patent: 5936868 (1999-08-01), Hall
patent: 6410972 (2002-06-01), Sei et al.
patent: 6525350 (2003-02-01), Kinoshita et al.
patent: 11-214662 (1999-08-01), None
patent: 2000-269346 (2000-09-01), None
Kasem, M.; “A new generation of interconnect technology for high performance electronics”, Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT, Oct. 18-19, 1999,Page(s).: 440-447.

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