Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2005-06-07
2005-06-07
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S233500
Reexamination Certificate
active
06903983
ABSTRACT:
A semiconductor integrated circuit device includes a first memory cell array corresponding to bank0, a second memory cell array corresponding to bank1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank0or bank1and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.
REFERENCES:
patent: 6111787 (2000-08-01), Akaogi et al.
patent: 6320800 (2001-11-01), Saito et al.
patent: 6324115 (2001-11-01), Choi
patent: 2004/0001366 (2004-01-01), Peronni et al.
patent: 2001-52495 (2001-02-01), None
Hara Tokumasa
Honda Yasuhiko
Kato Hideo
Saito Hidetoshi
Shiga Hitoshi
Elms Richard
Kabushiki Kaisha Toshiba
Nguyen Hien
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