Semiconductor integrated circuit device and process for manufact

Details Semiconductor integrated circuit device and process for manufact Semiconductor integrated circuit device and process for manufact

1995-05-25

1998-05-19

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 327566, 257390, G11C 1100, H01L 2500, H01L 2976

Patent

active

057544670

ABSTRACT:
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

REFERENCES:
patent: 5051958 (1991-09-01), Arakawa
patent: 5406107 (1995-04-01), Yamaguchi
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5523598 (1996-06-01), Watanabe et al.
D. Chen, et al. "A New Device Interconnect Scheme for Sub-Micron VLSI", Hewlett Packard Laboratories, IEDM 84, pp. 118-121.
T. Tang et al., "VLSI Local Interconnect Level Using Titanium Nitride", Semiconductor Process and Design Center, IEDM 1985, pp. 590-593.

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