Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-07
2001-12-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S296000, C257S284000, C257S350000, C257S382000, C257S383000, C257S384000
Reexamination Certificate
active
06329680
ABSTRACT:
FIELD OF THE INVENTION
In general, the present invention relates to a semiconductor integrated circuit device and a process for manufacturing the same. More particularly, the present invention relates to an effective process which is applicable to a logic-DRAM(Dynamic Random Access Memory) mixture semiconductor integrated circuit device.
BACKGROUND OF THE INVENTION
In a logic-DRAM mixture LSI (Large Scale Integrated Circuit), since the wiring resistance of a logic portion has a big effect on the operating speed of the circuit, a metallic film having a low resistance is used as a wiring material. Examples of such a metallic film are an aluminum (Al) alloy film and a copper (Cu) film. The thickness of the wiring film is typically in the range 0.5 to 1.0 &mgr;m and the sheet resistance is in the range 35 to 70 m&OHgr;/□.
However, restrictions imposed by the fabrication processes, such as the photographic solution and the etching controllability impose a lower limit on wiring gaps and an upper limit on the number of lines. Thus, even if a plurality of lines M
1
, M
2
and M
3
are provided the semiconductor areas constituting a source and a drain of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), only one contact hole
67
can be created in each semiconductor area serving as the source and each semiconductor area serving as the drain in some cases, as shown in FIG.
7
. Thus, deterioration of the operating characteristics of the MISFET, such as a decreased drain current caused by a parasitic drain-source resistance, raises a concern. For this reason, the surfaces of the semiconductor areas constituting the source and the drain are silicided to reduce the parasitic drain-source resistance.
It should be noted that a MISFET wherein the surfaces of the semiconductor areas thereof constituting the source and the drain are silicided is described for example in Semiconductor World, a publication issued by Press Journal Corporation, the edition of December 1995, pages 150 to 151.
SUMMARY OF THE INVENTION
In a logic-DRAM mixture LSI, after a MISFET of the logic portion has been formed, a capacitive element of the DRAM portion for storing information is created. For this reason, due to a heat-treatment process carried out on the semiconductor substrate in the process of creating the capacitive element of the DRAM portion for storing information, a chemical reaction of a silicide layer will proceed on the surfaces constituting the source and the drain of the MISFET of the logic portion. As a result, it is quite within the bounds of possibility that problems, such as peeling off of the silicide layer, an increased source-drain sheet resistance and increased junction leakage between the source and the drain, will arise.
In addition, since a silicide layer is formed by a chemical reaction of a metal, such as a titan (Ti) film or a cobalt (Co) film, and silicon comprising a semiconductor substrate, the matching of a shallow junction between the source and the drain is poor in spite of the fact that good matching is absolutely required for increasing the performance of the MISFET. There is a conceivable method to improve the matching whereby the thickness of the silicide layer is reduced. However, this method will raise a problem of an increased source-drain parasitic resistance.
It is thus an object of the present invention to provide a technology that is capable of preventing the operating characteristic of a semiconductor integrated circuit device from deteriorating by reducing the parasitic resistance of a MISFET of the device.
Other objects and characteristics of the present invention will become apparent from the following description of the present invention when taken with reference to the accompanying drawings.
Overviews of representative aspects of the present invention as disclosed in this specification will be described briefly as follows.
(1) In the logic portion of the logic-DRAM mixture of the semiconductor integrated circuit device provided by the present invention, a plurality of first contact holes reaching a semiconductor area used as a source of a MISFET and a plurality of second contact holes reaching a semiconductor area used as a drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET, the semiconductor area used as the source is shunted through the first contact holes by first conductive films on the same layer as bit lines and the semiconductor area used as the drain is shunted through the second contact holes by second conductive films also on the same layer as the bit lines.
(2) According to a method of fabricating a logic-DRAM mixture semiconductor integrated circuit device provided by the present invention, in a process to create a MISFET of a logic portion of the device, first of all, after the creation of the MISFET including a pair of a source and a drain formed to comprise a gate insulation film, a gate electrode and a semiconductor area created on the main surface of a semiconductor substrate, a first insulation layer is created over the MISFET. Then, after a plurality of first contact holes reaching a semiconductor area used as a source and a plurality of second contact holes reaching a semiconductor area used as a drain are bored through the first insulation layer, plugs are created through the first and second contact holes. Subsequently, the semiconductor area used as the source is shunted through the plugs inside the first contact holes by first conductive films on the same layer as bit lines and the semiconductor area used as the drain is shunted through the plugs inside the second contact holes by second conductive films also on the same layer as the bit lines. Then, after a second insulation layer has been created over the bit lines, a first through hole reaching the first conductive film and a second through hole reaching the second conductive film are bored through the second insulation layer. Finally, plugs are created through the first and second through holes, and an upper wiring layer is then formed.
According to the features described above, a semiconductor area used as the source of a MISFET is shunted through first contact holes by first conductive films on the same layer as bit lines and, by the same token, a semiconductor area used as the drain of the MISFET is shunted through second contact holes by second conductive films also on the same layer as the bit lines. Thus, most of the drain current of the MISFET flows through the shunting first and second conductive films, reducing the source-drain parasitic resistance. As a result, the operating characteristics of the MISFET can be prevented from deteriorating. In addition, since the parasitic resistance can be reduced, it is possible to eliminate a process to create a silicide layer on the surfaces of the semiconductor areas used as the source and the drain and, hence, to make the fabrication process simpler.
REFERENCES:
patent: 5237187 (1993-08-01), Suwanai et al.
patent: 6020643 (2000-02-01), Fukuzumi et al.
patent: 6066881 (2000-05-01), Shimizu et al.
patent: 6078072 (2000-06-01), Okudaira et al.
patent: 6194757 (2001-02-01), Shinkawata
patent: 10275910 (1998-10-01), None
“Metallization of the 0.25&mgr;m generation”, Monthly Semiconductor World 1995.12, pp. 150-151.
Asaka Katsuyuki
Takakura Toshihiko
Yoshida Makoto
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Eddie
Ortiz Edgardo
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