Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1998-09-01
2000-03-07
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523001, 365233, H01L 2702
Patent
active
060349123
ABSTRACT:
A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.
REFERENCES:
patent: 4780846 (1988-10-01), Tanake et al.
patent: 5040152 (1991-08-01), Voss et al.
patent: 5097450 (1992-03-01), Toda et al.
patent: 5150330 (1992-09-01), Hag
patent: 5280450 (1994-01-01), Nakagome et al.
patent: 5386387 (1995-01-01), Tanizaki
patent: 5512766 (1996-04-01), Kusunoki et al.
Kubo, Seiji. "BiCMOS Technology", Sep. 20, 1990, pp. 146-151 (Provided in Japanese w/English translation attached).
Nikkei Electronics, Nikkei-McGraw-Hill, Sep. 9, 1985, pp. 165-169 & 175-176 (Provided in Japanese w/English translation attached).
Higeta Keiichi
Isomura Satoru
Ito Yuko
Kobayashi Tohru
Miyazawa Kengo
Hitachi , Ltd.
Nguyen Viet Q.
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