Semiconductor integrated circuit device and method of...

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Reexamination Certificate

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C365S189050, C257S326000, C257S365000

Reexamination Certificate

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11117721

ABSTRACT:
A semiconductor integrated circuit device comprises a first transistor formed on a bulk substrate region in a semiconductor substrate and having a source or drain layer connected to a first reference voltage; and a second transistor including an impurity layer region formed on the bulk substrate region and being of a conductivity type different from that of the bulk substrate region, a semiconductor region formed on the impurity layer region and being of a conductivity type the same as that of the bulk substrate region, a source layer and a drain layer formed in the semiconductor region and being of a conductivity type different from that of the bulk substrate region, a gate insulating film provided between the source layer and the drain layer and formed on the semiconductor region, a gate electrode formed on the gate insulating film, and a body region surrounded by the source layer, the drain layer, the impurity layer region, and the gate insulating film on a section along a source-drain direction and being of a conductivity type the same as that of the bulk substrate region, the impurity layer region being depleted, wherein the source layer or the drain layer of the second transistor is connected to the first reference voltage through the first transistor.

REFERENCES:
patent: 4819043 (1989-04-01), Yazawa et al.
patent: 5583361 (1996-12-01), Morishita
patent: 6424011 (2002-07-01), Assaderaghi et al.
patent: 2002/0093064 (2002-07-01), Inaba
patent: 2002-289850 (2002-10-01), None
S. Inaba et al., “Silicon on Depletion Layer FED (SODEL FED) for Sub-50 nm High performance CMOS Applications: Novel Channel and S/D Profile Engineering Schemes by Selective Si Epitaxial Growth Technology”, IEDM, 2002, pp. 659-662.
Y. Tsukamoto et al., “Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts To Achieve High Speed, Low, Power SRAM Cells”, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, 2003, pp. 22-23.

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