Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-11-27
2004-05-25
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C327S540000
Reexamination Certificate
active
06741118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices in which the stability of the negative voltage generated by a negative voltage generating circuit is increased, and methods of manufacturing such semiconductor integrated circuit devices.
2. Description of the Related Art
As manufacturing processes have become progressively miniaturized in recent years, there has arisen a need for system LSIs for specific applications that include dynamic random access memories (hereinafter, abbreviated as DRAM) and for which standard CMOS manufacturing processes can be used.
Conventionally, the negative voltage (VBB voltage) generated by a negative voltage generating circuit in the DRAM has been used as the well voltage of memory cell portions employing a triple well structure. Planar memory cell structures have been adopted as a way to form DRAMs through standard CMOS processing, as mentioned above, without the use of a triple well.
Here,
FIG. 11
shows a planar memory cell structure. Numeral
300
denotes a p-type semiconductor substrate connected to a ground voltage VSS. An n-well
310
is formed in the upper portion of the p-type semiconductor substrate
300
, and in the upper portion of the n-well
310
are formed a high-concentration n-type diffusion layer
320
and high-concentration p-type diffusion layers
330
. A VDD power source is connected via the high-concentration n-type diffusion layer
320
, and a bit line BL is connected to one of the high-concentration p-type diffusion layers
330
. A gate
340
is a word line WL with an internally stepped down power source VINT as its power source. The two high-concentration p-type diffusion layers
330
and the gate
340
together make up a PMOS access transistor
360
. The high-concentration p-type diffusion layer
330
to which the bit line BL is not connected and a memory cell plate
350
connected to VBB make up a PMOS memory cell capacitor
370
.
This memory cell operates as follows. The PMOS access transistor
360
is activated by setting the gate
340
, that is, the word line WL, to the ground voltage VSS, and data are written by injecting a charge from the bit line BL into the channel region formed near the surface of the n-well
310
below the memory cell plate
350
.
FIG. 12
is an equivalent circuit of this planar memory cell structure.
As shown in
FIGS. 11 and 12
, the VDD power source, which is a positive voltage, is used for the well voltage of the memory cell portion in which the PMOS access transistor
360
is employed, and the VBB voltage, which is a negative voltage, is used as the memory cell plate power source for the PMOS memory cell capacitor
370
.
Next, a conventional semiconductor memory device with the above planar memory cell structure is described.
FIG. 13
is a block diagram of the conventional semiconductor memory device. Numeral
410
denotes a VBB voltage generating circuit and
480
denotes a memory cell array having a memory cell plate with a negative charge. The VBB voltage generating circuit
410
includes a charge pump circuit
420
for generating VBB voltage, a ring oscillator
430
for generating pulse signals that cause the charge pump circuit
420
to perform a charge pump operation, a VBB voltage detection circuit
450
to which the VBB voltage is fed back and which generates signals (BBDOWN) for activating the ring oscillator
430
, and a constant voltage generating circuit
460
for generating a reference voltage that is used by the VBB voltage detection circuit
450
. The VBB voltage detection circuit
450
is made of a comparison voltage generating circuit
451
and a non-inverting amplifier
454
for lowering the VBB voltage.
The comparison voltage generating circuit
451
is a series circuit of a resistor R
21
and a resistor R
22
. One terminal of the resistor R
21
is connected to a node of a constant voltage VREG output from the constant voltage generating circuit
460
, and the other end is connected to one terminal of the resistor
22
and is also connected to a node of a comparison voltage VCOMP that is applied to a non-inverting input terminal (+) of the non-inverting amplifier
454
for lowering the VBB voltage. The other end of the resistor R
22
is connected to the VBB node.
The operation of the semiconductor memory device configured as above is described below. The non-inverting amplifier
454
has two input terminals and one output terminal. As mentioned above, the comparison voltage VCOMP is applied to the non-inverting input terminal (+) and a reference voltage VREF (in the present conventional example, the ground voltage VSS) is applied to the inverting input terminal (−). Consequently, if the VCOMP voltage is higher than the reference voltage VREF, that is, the ground voltage VSS, then a voltage of the BBDOWN node, which is the output, become a logic ‘HIGH’ voltage (hereinafter, referred to simply as HIGH voltage), and if the VCOMP voltage is lower than the ground voltage VSS, then the BBDOWN node becomes a logic ‘LOW’ voltage (hereinafter, referred to simply as LOW voltage).
When the BBDOWN voltage is HIGH voltage, the ring oscillator
430
self-oscillates, and the charge pump circuit
420
that receives this oscillated pulse executes a pumping operation that causes the VBB voltage to drop. On the other hand, when the BBDOWN voltage is LOW voltage, the ring oscillator
430
does not self-oscillate, and the operation of the charge pump circuit
420
is stopped.
The VCOMP voltage is determined by the voltage division ratio of the resistor R
21
and the resistor R
22
, and is expressed by Equation (1).
VCOMP=VBB+{R
22
(
VREG−VBB
)}/(
R
21
+
R
22
) (1)
If the resistor voltage division ratio determined by the resistor R
21
and the resistor R
22
is such that the VCOMP voltage is equal to the VREF (VSS) voltage when the VBB voltage is a desired voltage, the VBB voltage can be maintained at the desired voltage.
However, with the aforementioned conventional semiconductor memory device, although the VBB voltage can be actively lowered by activating the charge pump circuit, there is no function for raising the VBB voltage. Originally, if left free, the VBB voltage rises naturally due to leakage current, for example, in due time. Moreover, because the requirements for voltage control of the VBB current were not particularly stringent (for example, about ±50 mV fluctuation), it was adequate to provide only a function for lowering the VBB voltage.
As mentioned above, however, if the VBB voltage, which is a negative voltage, is used as the plate power source of the memory cell capacitor, then more stringent voltage control for the VBB voltage (for example, about ±10 mV fluctuation) becomes necessary. Also, ordinarily, due to reductions in power, the ability of the VBB voltage generating circuit to supply negative current is limited, that is, there is a high output impedance. Thus, when writing data to the memory cell capacitor, the memory cell plate voltage fluctuates due to capacitive coupling. If the VBB voltage rises due to this capacitive coupling, the VBB voltage can be lowered to the set voltage by operating the charge pump circuit. However, if VBB falls below the set voltage, it takes time for the VBB voltage to return to the set voltage, because the conventional VBB voltage generating circuits do not have a function for lowering the voltage. If data are read out from the memory when the VBB voltage is lower than the set voltage, the read voltage becomes low due to coupling, and this is problematic because it leads to the read out of erroneous data.
The above problem is not limited to semiconductor memory devices, and is common to general semiconductor integrated circuit devices having a configuration in which negative voltage (VBB voltage) generated by a negative voltage generating circuit is supplied.
SUMMARY OF THE INVENTION
Therefore, in light of the foregoing conventional problems, it is an object of the present invention
Ohta Kiyoto
Origasa Kenichi
Uchikoba Toshitaka
Yamasaki Yuji
Cunningham Terry D.
Matsushita Electric - Industrial Co., Ltd.
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