Semiconductor integrated circuit device and method for...

Details Semiconductor integrated circuit device and method for... Semiconductor integrated circuit device and method for...

2005-03-22

2005-03-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06871338

ABSTRACT:
A method for designing a semiconductor integrated circuit device, the method has the steps of producing, for a plurality of placement regions on each of which a design pattern is to be placed, first layout data having a first expected value based on a first layout design rule, producing, if a difference between the first expected data and an expected finished size after fabrication of the first layout data falls within an error tolerance for a standard value, first OPC data by correcting the first layout data, producing, if the plurality of placement regions include an out-of-tolerance region for which the first OPC data falling within the error tolerance cannot be produced, second layout data having a second expected value for the out-of-tolerance region based on a second layout design rule, producing second OPC data by correcting the second layout data such that an expected finished size after fabrication of the second layout data falls within the error tolerance for the standard value, and producing mask data by using the first OPC data and the second OPC data.

REFERENCES:
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6282696 (2001-08-01), Garza et al.
patent: 6470489 (2002-10-01), Chang et al.
patent: 6553559 (2003-04-01), Liebmann et al.
patent: 6625801 (2003-09-01), Pierrat et al.
patent: 20010023043 (2001-09-01), Futrell et al.

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