Semiconductor integrated circuit device and manufacturing...

Details Semiconductor integrated circuit device and manufacturing... Semiconductor integrated circuit device and manufacturing...

2005-03-08

2005-03-08

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

62

Reexamination Certificate

active

06864169

ABSTRACT:
After formation of Cu interconnections46ato46eeach to be embedded in an interconnection groove40of a silicon oxide film39by CMP and then washing, the surface of each of the silicon oxide film39and Cu interconnections46ato46eis treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

REFERENCES:
patent: 3837929 (1974-09-01), Caule
patent: 4910169 (1990-03-01), Hoshino
patent: 5244534 (1993-09-01), Yu et al.
patent: 5281304 (1994-01-01), Kadomura
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5395801 (1995-03-01), Doan et al.
patent: 5447887 (1995-09-01), Filipiak et al.
patent: 5677244 (1997-10-01), Venkatraman
patent: 5693563 (1997-12-01), Teong
patent: 5744376 (1998-04-01), Chan et al.
patent: 5770095 (1998-06-01), Sasaki et al.
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5875507 (1999-03-01), Stephens et al.
patent: 5932486 (1999-08-01), Cook et al.
patent: 5972792 (1999-10-01), Hudson
patent: 6016000 (2000-01-01), Moslehi
patent: 6043153 (2000-03-01), Nogami et al.
patent: 6048789 (2000-04-01), Vines et al.
patent: 6068879 (2000-05-01), Pasch
patent: 6083840 (2000-07-01), Mravic et al.
patent: 6117775 (2000-09-01), Kondo et al.
patent: 6117783 (2000-09-01), Small et al.
patent: 6136680 (2000-10-01), Lai et al.
patent: 6143658 (2000-11-01), Donnelly, Jr. et al.
patent: 6146135 (2000-11-01), Watanabe et al.
patent: 6153043 (2000-11-01), Edelstein et al.
patent: 6153523 (2000-11-01), Van Ngo et al.
patent: 6159857 (2000-12-01), Liu et al.
patent: 6165894 (2000-12-01), Pramanick et al.
patent: 6171957 (2001-01-01), Maekawa
patent: 6174810 (2001-01-01), Islam et al.
patent: 6181012 (2001-01-01), Edelstein et al.
patent: 6191007 (2001-02-01), Matsui et al.
patent: 6207552 (2001-03-01), Wang et al.
patent: 6242349 (2001-06-01), Nogami et al.
patent: 6326299 (2001-12-01), Homma et al.
patent: 6348402 (2002-02-01), Kawanoue et al.
patent: 6355571 (2002-03-01), Huang et al.
patent: 6376345 (2002-04-01), Ohashi et al.
patent: 6521532 (2003-02-01), Cunningham
patent: 6596637 (2003-07-01), Schonauer et al.
patent: 20010030367 (2001-10-01), Noguchi et al.
patent: 20020027287 (2002-03-01), Takagi et al.
patent: 20020042193 (2002-04-01), Noguchi et al.
patent: 0 508 156 (1992-10-01), None
patent: 5-47735 (1993-02-01), None
patent: 6-37038 (1994-02-01), None
patent: 6-224194 (1994-08-01), None
patent: 6-283520 (1994-10-01), None
patent: 7-135192 (1995-05-01), None
patent: 9-82798 (1997-03-01), None
patent: 9-306915 (1997-11-01), None
patent: 10-56014 (1998-02-01), None
patent: 10-214834 (1998-08-01), None
patent: 10-261715 (1998-09-01), None
patent: 11-16912 (1999-01-01), None
patent: 11-87353 (1999-03-01), None
patent: 11-135466 (1999-05-01), None
patent: 11-251317 (1999-09-01), None
patent: 11-330246 (1999-11-01), None
patent: 2000-12543 (2000-01-01), None
patent: 2000-150435 (2000-05-01), None
patent: 2000-183000 (2000-06-01), None
patent: 2000-277612 (2000-10-01), None
patent: 2000-290637 (2000-10-01), None
patent: 2000-306873 (2000-11-01), None
patent: 2001-9701 (2001-01-01), None
patent: 2001-31950 (2001-02-01), None
patent: 2001-298009 (2001-10-01), None
B. Luther et al., “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices”, VMIC Conference 1993 ISMIC-102/93/0015, Jun. 8-9, 1993, pp. 15-21.
J. Noguchi et al., “TDDB Improvement in Cu Metallization under Bias Stress”, IEEE 38thAnnual International Reliability Physics Symposium, 2000, pp. 339-343.
S. Matsushita, “The Lighting in Clean Rooms Induces the Corrosion of Copper: Hitachi Announces the Mechanism for Photo-Corrosion”, Semiconductor FPD World, Jul. 2000, pp. 69-73 (translation attached).
Y. Homma et al., “Control of Photocorrosion in the Copper Damascene Process”, Journal of the Electrochemical Society, 147 (3), 2000, pp. 1193-1198.
T. Ohmura et al., “CMP Device ‘SP4000’”, Electronic Materials, May 1996, pp. 53-55 (translation attached).
M. Tsujimura, “Clean CMP System”, Electronic Materials, May 1996, pp. 62-65 (translation attached).
U.S. patent application Ser. No. 09/527,751, Imai et al., filed Mar. 17, 2000.
U.S. patent application Ser. No. 09/646,671, Uno et al., filed Jun. 21, 2000.
Y. Hirakura, “CMC Device ‘Avanti-472’”, Electronic Materials, May 1996, pp. 33-35 (translation attached).
T. Kawane, “Etching Low-k Films—Improving Resistance to Heat and O2Plasma is the Key to Successfully Applying Organic Films to the Cu-Damascene Process”, Semiconductor World, Nov. 1998, pp. 74-76 (translation attached).

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