Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-28
2007-08-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10609572
ABSTRACT:
A semiconductor integrated circuit device includes macros and area I/Os. The macros are arranged in optional locations of a first empty area of a gate area in a center portion of a chip, respectively. Each of the area I/Os contains a plurality of area I/O buffers, and is arranged in an optional location of a second empty area of a total area of the gate area and a buffer area in a circumferential portion of the chip. A first macro of the macros is connected with a specific one of the area I/Os. Here, the specific area I/O may be related to the first macro and be arranged in relation to a location for the first macro to be arranged.
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patent: 4-171756 (1992-06-01), None
I/O floorplanning Guide for SA-12 (International Business Machines Corporation, ASIC Products Application Note No. SA14-2309-00, 1998).
Do Thuan
NEC Electronics Corporation
Young & Thompson
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