Semiconductor integrated circuit device and its manufacturing me

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257774, 257208, 257209, 257211, 257296, 257903, H01L 2348, H01L 2352, H01L 2940

Patent

active

060668962

ABSTRACT:
On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

REFERENCES:
patent: 5195053 (1993-03-01), Hayano
patent: 5219639 (1993-06-01), Sugawara et al.
patent: 5512514 (1996-04-01), Lee
patent: 5869901 (1999-02-01), Kusuyama

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