Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2002-05-14
2004-10-19
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S046000, C327S202000, C714S726000
Reexamination Certificate
active
06806731
ABSTRACT:
CLAIM OF PRIORITY
This application claims priority to Japanese Patent Application No. 2001-151983 filed on May 22, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and, more particularly, the present invention relates to a semiconductor circuit device which has a logic circuit including storage elements and a fault-detecting method of a semiconductor integrated circuit device.
2. Description of the Background
A conventional method for scanning a logical circuit has been widely used to detect faults, such as a stuck-at fault, in a logic circuit. This conventional method can efficiently detect faults because the value of a flip-flop (hereinafter, “FF”) can be directly handled using this method.
The process for detecting a fault (hereinafter, “testing”) of a scanned logic circuit will now be explained with reference to the accompanying drawings.
FIG. 17
is a circuit diagram showing a scan FF as used in the prior art. This example is a scan FF with a multiplexer (hereinafter, “MUX”), or a MUX-type scan flip-flop (FF).
In this configuration, MUX g
1702
is connected with input terminal D of a master latch g
1701
constituting a FF. A signal (hereinafter, “input signal from logic circuit”) which comes from logic gates (hereinafter, “user logic circuit”) for normal operation at the preceding stage is input through an input signal line into g
1702
. Also, a signal for scan from the FF at the preceding stage (hereinafter, “scan-in signal”) is input through a scan-in signal line. Further, a control signal for selecting whether g
1701
picks up the input signal from logic circuit or the scan-in signal (hereinafter, “scan-enable signal”) is input through a scan-enable signal line. Input terminal D of a slave latch g
1703
is connected with output terminal Q of g
1701
. The output terminal of g
1703
is connected with an output signal line which conveys a signal (hereinafter, “output signal”) to the user logic circuit or a scan FF in a successive stage.
FIG. 18
shows a logic circuit which is scanned using the prior art. This is an example of a scanned logic circuit in which multiple MUX-type scan FFs are connected. In this configuration, scan-out signal lines of MUX-type scan FFs g
1801
, g
1802
are connected with the scan-in signal lines of g
1802
and g
1803
, respectively; this constitutes a signal path (hereinafter, “path”). This path is referred to as a “scan path.”
The scan-in signal line of g
1801
is connected with the terminal (hereinafter, “scan-in terminal”) for inputting a scan-in signal from the outside of the semiconductor integrated circuit chip while the scan-out signal line of g
1803
is connected with the terminal (hereinafter, “scan-out terminal”) for outputting a scan-out signal to the outside of the semiconductor integrated circuit chip (hereinafter, “chip”).
A test procedure which utilizes scan FFs preferably takes place in the following sequence: (1) an operation for substituting an initial value for the test into each FF in the logic circuit (“scan-in operation”); (2) an operation for inputting the initial value from each FF into the user logic circuit and letting each FF pick up the result data for the test as an output from the user logic circuit (“testing operation”); and (3) an operation for collecting the result data from each FF (“scan-out operation”). This sequence may be repeated. In
FIG. 18
, a
1804
, a
1805
, and a
1806
represent signal flows for scan-in operation, testing operation, and scan-out operation, respectively.
FIG. 19
is a timing diagram showing the operation of a scan FF (g
1704
) as used in the prior art. First, for the scan-in operation, a scan-enable signal is set at High in order to enable each FF to pick up a scan-in signal. Also, in order to substitute the initial value for a test value in each FF, a transition of the system clock signal is made more than one time (s
1901
) to perform shift operations through the scan path.
Next, for the testing operation, in order to enable each FF to pick up an output signal, the scan-enable signal is set at Low (s
1902
). Also, a transition of the system clock signal is made a first time to input the initial value for the test into the user logic circuit and a second time for the result data for the test to be picked up by each FF (s
1903
).
For the scan-out operation, the scan-enable signal is set at High again in order to enable each FF to output a scan-out signal (s
1904
). Also, for collection of the result data for the test from each FF, a shift operation is done as in the scan-in operation.
FIG. 20
is a circuit diagram showing an exemplary internal circuit of a scan FF (g
1704
) as used in the prior art.
However, in a scan-in operation and a scan-out operation (collectively referred to as “scan operation”) the amount of state changes of the logic circuit tends to be higher than in normal user operation. Therefore, as pointed out in IEEE Computer vol.32, no.11 (p.61, 1999), with the growing tendency toward device miniaturization, fault-detecting errors due to excessive voltage drops or chip damage due to heat generation may occur.
As potential solutions to address this problem, some methods have been suggested; the Proceedings of the 11
th
International VLSI Test Symposium (pp.4-9, 1993) include one such method in which the logic circuit is divided into blocks which are then tested sequentially.
The way in which the logic circuit is divided into blocks and each block is tested will now be described with reference to the relevant accompanying drawings.
FIG. 21
shows a logic circuit which is divided according to the prior art. In this example, the logic circuit is divided into N blocks using N+1 scan paths which consist of MUX-type scan FFs (wherein N is a natural number).
In this configuration, a selector g
2102
which controls the operation of Logic
1
at the following stage is connected with the output signal line of a scan FF g
2101
. An output signal for normal operation and testing operation which comes from g
2101
is input into g
2102
. In addition, a fixed signal for pausing Logic
1
is input through a boundary scan (FF) g
2103
. Further, a signal (pausing signal) for selecting whether to output the output signal from g
2101
or the fixed signal through g
2103
to Logic
1
is input through Pausing Signal Line
1
. The same type of selector is connected with the output signal lines of the other scan FFs to control the operation of Logic
1
through Logic N.
FIG. 22
is a timing diagram showing the operation of the logic circuit which is divided according to the prior art. Prior to the testing operation for Logic
1
, Pausing Signal
1
is set at Low so that the initial value for the test as supplied from Scan-In Signal Line
1
can be input for Logic
1
(s
2201
). For pausing Logic
2
to Logic N, Pausing Signal
2
to Pausing Signal N are set at High (s
2202
). Thereafter during the testing operation for Logic
1
, the result data for the test of Logic
1
is stored in the scan FF connected with Scan-In Signal Line
2
. Next, the result data for the test of Logic
1
is collected by scan operation (s
2203
). This is followed by similar operation sequences for Logic
2
through Logic N.
Regardless, since there are overlaps of scan operations by scan FFs in the boundaries of the divided logic circuit, this method requires a longer test time. This counteracts the advantage of scanning because the time required for scan operation generally accounts for most of the overall test time.
As exemplified in
FIG. 22
, although a scan operation which uses Scan-In Signal Line
2
as an input can be accomplished during the test of Logic
1
(s
2204
), it must be done again during the test of Logic
2
(s
2205
). This results in an increase in the cost required for the test (the “test cost”).
As another potential solution, “Design for At-speed Test, Diagnosis and Measurement” (Kluwer Academic Publishers, p.24, 1999) suggests a method of decreasing the frequency in scan operation to reduce power consu
A. Marquez, Esq. Juan Carlos
Chang Daniel D.
Fisher Esq. Stanley P.
Reed Smith LLP
Renesas Technology Corp.
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