Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-04-10
2007-04-10
Tran, Long K. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S188000, C257SE21630
Reexamination Certificate
active
11136710
ABSTRACT:
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.
REFERENCES:
patent: 6255123 (2001-07-01), Reis
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: WO2002/043151 (2002-05-01), None
Y. Nakahara et al.; “A Robust 65-nm Node CMOS Technology for Wide-range Vdd Operation”, 2003 IEEE.
A. Shimizu et al.; “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, 2001 IEEE.
Hatada Akiyoshi
Katakami Akira
Shima Masashi
Shimamune Yosuke
Tamura Naoyoshi
Fujitsu Limited
Tran Long K.
Westerman, Hattori, Daniels & Adrian , LLP.
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