Semiconductor integrated circuit device and error checking...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C714S762000

Reexamination Certificate

active

10878229

ABSTRACT:
A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

REFERENCES:
patent: 5127014 (1992-06-01), Raynham
patent: 6065146 (2000-05-01), Bosshart
patent: 6216246 (2001-04-01), Shau
patent: 7117421 (2006-10-01), Danilak
patent: 2002/0184592 (2002-12-01), Koga et al.
patent: 10-177800 (1998-06-01), None
patent: 2003-59290 (2003-02-01), None

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