Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-08
2010-11-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07844922
ABSTRACT:
In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided, a logic function is allotted to the cells, the number of series connection stages of the cells within an evaluation period determined by a clock cycle of the clock signal is found, and a judgment is made as to whether restrictions can be met by arranging the cells on the semiconductor integrated circuit device and performing delay calculations in a case where the number of series connection stages does not exceed a prescribed number of stages. When the restrictions are met, the whole processing comes to an end. When the restrictions are not met, modifications are made.
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Chiang Jack
Nec Corporation
Sughrue & Mion, PLLC
Tat Binh C
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