Semiconductor integrated circuit device and data-write...

Details Semiconductor integrated circuit device and data-write... Semiconductor integrated circuit device and data-write...

2001-09-07

2003-02-25

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S189011

Reexamination Certificate

active

06525975

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to technique of data-write on memory cells for a semiconductor integrated circuit. More particularly, it relates to enhancement of low power consumption, or high-speed operation, and stable operation during data-write operation.
2. Description of Related Art
With the recent progress of computer technology, there has been needed a memory usable for graphic processing purpose such as three dimensional animation pictures wherein address cycle changes irregularly. In other words, high-speed random access performance is required for a memory regardless of data-readout cycle and data-write cycle. However, this kind of high-speed random access performance is not feasible for synchronous type semiconductor memory devices such as dynamic random access memory (referred to as DRAM hereinafter) and synchronous type DRAM (SDRAM, hereinafter) that multiplex row address and column address and input the addresses with different timing.
As a high-speed memory that can realize high-speed cycle time performance of static random access memory (SRAM, hereinafter) while making the most use of high circuit integration design of DRAM and SDRAM, there has been devised a memory that inputs data without multiplexing addresses and determines whether readout cycle or write cycle within a command. Fast Cycle RAM, or FCRAM (Registered Trademark), is a noticeable example of that.
A memory cell section M
1000
in
FIG. 9
shows the structure of a high-speed memory. For concise description,
FIG. 9
shows a part of the memory, or indispensable structural elements thereof. Memory cells Ta, Tb, Tc, and Td are connected to bit lines /BL, /BLM, BL, BLM, respectively. Data stored in the memory cells Ta, Tb, Tc, and Td are readout as stored charges. After redistributed to the respective bit lines BL, /BL, BLM, /BLM, the stored charges are amplified by sense amplifiers SA, and SAM with being coupled as bit line pair BL, /BL and bit line pair BLM, /BLM. The amplified data are delivered to data bus lines DB, and /DB through column switches TN
1
, TN
2
, TN
3
, and TN
4
, and then, amplified by a read amplifier RA and outputted from an input/output buffer Buf (from Dout). On the contrary, input data Din are amplified by a write amplifier WA through the input/output buffer Buf, and then, stored in memory cells Ta, Tb, Tc, and Td as charges through bit lines BL, /BL and BLM, /BLM from the data bus lines DB, and /DB.
Out of the memory cells Ta, Tb, Tc and Td, selection of memory cells to be connected the bit line pairs BL, /BL and BLM, /BLM is made by an active signal ACT and a precharge signal PRE transmitted from a row control circuit RC that has received a command signal CMD. More specifically, the active signal ACT and the precharge signal PRE make a word decoder WD active/inactive so as to make signal level of word lines WL and WLM high level. Furthermore, a sense amplifier signal circuit SC controls activation signal LE for the sense amplifiers SA and SAM based on the active signal ACT and the precharge signal PRE. Thereby, the sense amplifiers SA and SAM are made active/inactive. Still further, a column control circuit CC outputs a control signal ACL based on a command signal CMD from the row control circuit RC. Then, a column switch signal circuit Cs controls switch signals CL, and CLM, whereby column switches TN
1
, TN
2
, TN
3
and TN
4
are made conductive
onconductive.
FIG. 10
shows a waveform diagram of readout operation and
FIG. 11
shows that of write operation. A command signal CMD activates the row control circuit RC to output an active signal ACT. Owing to the active signal ACT, the word line WL from the word decoder WD is selected. Then, the memory cells Tc and Td are connected to the bit lines BL and BLM, respectively, and stored charges are redistributed to the bit lines BL and BLM. Up to this point, readout operation and write operation are in the same manner.
Firstly, readout operation will be described. Due to redistribution of stored charges, the bit lines BL and /BL both in equalized state begin to have potential differences gradually (this period is named Period {circumflex over (1)}. As to the bit lines BLM, and /BLM, operation is taken in the same manner as the bit lines BL, and /BL. Accordingly, the following explanation will be omitted. The Period {circumflex over (1)}means a period until the potential difference between the bit lines BL and/BL reaches amplification sensitivity of the sense amplifier SA. The potential difference at this point is of about several ten mV. After the Period {circumflex over (1)} terminates, an activation signal LE for the sense amplifier SA is set to high level. Thereby, the sense amplifier SA is driven to amplify the bit lines BL and /BL (this period is named Period {circumflex over (2)}. After the bit lines BL and /BL are amplified, the control signal ACL is set to high level so as to start up a switch signal CL with high level and readout data on the data bus lines DB and /DB (this period is named Period {circumflex over (3)}. Time that the switch signal CL is kept high level is optimized as the time needed to readout data from the bit lines BL and /BL to the data bus lines DB and /DB. It is the column control circuit CC that sets optimum time.
Next, write operation will be described. When the Period {circumflex over (1)} begins and the memory cell Tc is selected on condition that the memory cells Ta and Tc are connected to the bit lines BL and /BL, respectively, a switch signal CL is set to high level. Thereby, the data bus lines DB and /DB are connected to the bit lines BL and /BL, respectively. Then, the write amplifier WA begins write operation. Since this write operation is made with the switch signal CL being set, this period corresponds to the Period {circumflex over (3)} mentioned in the readout operation. Prompt write operation is required because some data must be inversed to obtain write data and also because the potential difference between the bit lines BL and/BL must reach amplification sensitivity of the sense amplifier SA before the Period {circumflex over (2)} begins. Load that the write amplifier WA must drive is significantly large. That is, the write amplifier WA must drive load for both the data bus lines DB, /DB and the bit lines BL, /BL. Driving ability of the write amplifier WA must be designed high enough to quickly finish data-write on the bit lines BL and /BL before the Period {circumflex over (2)} begins. Since setting time of the switch signal CL (Period {circumflex over (3)} is set by the column control circuit CC and length of the setting time is fixed, the Period {circumflex over (2)} sometimes begins before the Period {circumflex over (3)} terminates.
During write operation, the bit lines BLM and /BLM not subject to data-write exercises the above-mentioned readout operation.
During write cycle, the write amplifier WA needs to write data on the bit lines BL, /BL via the data bus lines DB, /DB, respectively, within a period to readout charges stored in cells (corresponding to the Period {circumflex over (1)} in FIG.
11
). That is, within such a short time as the Period {circumflex over (1)}, the write amplifier WA must drive the data bus lines DB, /DB and data bit lines BL, /BL up to a predetermined voltage. Accordingly, driving ability of the write amplifier WA must be designed sufficiently high. Owing to this, an area occupied by the write amplifier WA becomes large on a chip and along with that, power consumption becomes high. This can be an obstacle to trend of semiconductor integrated circuit device design such as higher circuit integration and lower power consumption.
Moreover, data written on the bit lines BL, /BL are amplified up to full amplitude by the sense amplifier SA during amplification period for the bit lines (corresponding to the Period {circumflex over (2)}. In the read operation, it is necessary to surely obtain a readout period (corresponding to the Period {circumflex over (1)}. That is, the bit lines BL, /BL are connecte

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device and data-write... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device and data-write..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and data-write... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3142868