Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-31
2004-10-26
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S304000, C257S305000, C257S306000, C257S307000, C257S308000, C257S309000
Reexamination Certificate
active
06809364
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a small semiconductor integrated circuit device having a large storage capacity. More particularly, the present invention relates to a dynamic random-access memory (hereinafter, abbreviated to “DRAM”) suitable for use in a high-degree integrated circuit device.
2. Description of the Related Arts
The degree of integration of DRAMs has been quadrupled in three years and demand for DRAMs has progressively increased owing to the recent booming demand for personal computers.
Memory cells of a DRAM are arranged in either a folded bit line arrangement or an open bit line arrangement.
FIG. 1
shows the typical layout of the memory cells of a DRAM of a typical folded bit line structure. In this DRAM, word lines and bit lines of a width F are arranged at pitches
2
F to arrange the memory cells in the least possible area. Two memory cells are formed in a laterally. elongate active region, and the two memory cells use a common longitudinally elongate bit line contact.
FIG. 2
shows the typical layout of the memory cells of a DRAM of a typical open bit line structure mentioned in “1993 Symposium on VLSI Circuits” p. 91. In this DRAM, word lines of a width F are arranged at pitches
2
f
, and bit lines of a width F are arranged at pitches
3
F. Let us examine a data read process of reading data from those DRAMs of two different bit line structures. When one of the word lines of the DRAM in the folded bit line structure is turned on, data can be read from the alternate bit lines. As shown in FIG.
3
(
a
), two paired bit lines connected to a sense amplifier are two adjacent bit lines in the same mat. Thus, the arrangement of the memory cells is called a folded bit line structure. When one of the word lines of the DRAM of the open bit line structure is turned on, data can be read from all the bit lines, and two paired bit lines are in different mats as shown in FIG.
3
(
b
). Whereas the driven word line coupled with the paired bit lines is common in the folded bit line structure, the same is not common in the open bit line structure. In terms of noise, word line driving noise is cancelled between the paired bit lines in the folded bit line structure and the same is not cancelled in the open bit line structure, which signifies that the folded bit line structure is unsusceptible to noise. Although the open bit line structure is susceptible to noise, it is a significant feature of the open bit line structure that the cells can be arranged in a small area. Whereas one cell needs an area of 8 F
2
in the folded bit line structure as shown in
FIG. 1
, one cell needs an area of 6 F
2
in the open bit line structure as shown in FIG.
2
.
In view of mass production, the reduction of the area of a chip, i.e., the reduction of the area of a region for memory cell arrangement, is very effective in reducing the cost of the product. From such a point of view, the open bit line structure is more desirable than the folded bit line structure. However, it is a problem in employing the open bit line structure how far the noise resistance of the open bit line structure can be improved. Practically, the open bit line structure has been employed in DRAMs of generations up to a 16 kB-generation. However, recent DRAMs of advanced generations employ the folded bit line structure.
A DRAM having memory cells arranged in the open bit line arrangement of a structure similar to that shown in
FIG. 2
is proposed in Japanese Patent Laid-Open No. Hei 07-066299. Although this prior art DRAM has a memory cell typical layout closely resembling the memory cell typical layout shown in
FIG. 2
, the bit lines of this DRAM are arranged at pitches
4
F. Thus, the lower electrode contact holes for capacitors are arranged at increased intervals to reduce current leakage across the memory cells.
The following problems reside in the foregoing prior art DRAMs.
The DRAM mentioned in “1993 Symposium on VLSI Circuits” has the following problems. As obvious from
FIG. 2
, the lower electrode contact holes
5
for the capacitors are close to the bit lines
3
. The so-called self-alignment techniques are essential to forming the lower electrode contact holes
5
for the capacitors so that the lower electrode contact holes
5
may not touch the bit lines
3
. A bit line forming process and those following the bit line forming process will be explained with reference to a section taken on line A—A in FIG.
2
. As shown in
FIG. 4
, bit line contact plugs
10
are formed and then a two-layer film of a tungsten film and a silicon nitride film for forming bit lines are deposited. The two-layer film is processed by a lithographic process and a dry etching process to form bit lines
11
as shown in
FIG. 5. A
silicon nitride film
1201
is deposited as shown in
FIG. 6
, and a layer insulating film
901
of silicon oxide is formed in a flat surface over the silicon nitride film
1201
. Lower electrode contact holes for the capacitors are formed by an etching process having a high silicon nitride selectivity. Then, plugs
13
are formed as shown in FIG.
7
. Thus, the lower electrode contact holes can be formed by a self-alignment contact hole forming technique so that the lower electrode contact do not touch the bit lines
11
. Even if a sufficient allowance is unavailable, the contact holes can be formed without increasing area by the self-alignment contact hole forming technique. However, the self-alignment contact hole forming technique has the following problems. The dielectric constant of silicon nitride is about twice that of silicon oxide. The self-alignment contact hole forming technique shown in
FIG. 7
surrounds the bit line
11
by silicon nitride
12
and
1201
and insulate the bit line
11
from the lower electrode plug by silicon nitride, which increases bit line capacitance. As mentioned above, the open bit line structure is more susceptible to noise than the folded bit line structure. Therefore, it is very important to reduce bit line capacitance when the open bit line structure is employed. Therefore, it is inappropriate to apply the self-alignment contact hole forming technique to fabricating a DRAM of the open bit line structure.
In the DRAM proposed in Japanese Patent Laid-Open No. Hei 07-066299, the memory cells are arranged in the open bit line arrangement similar to that shown in FIG.
2
and the bit lines are arranged at increased pitches to space the lower electrode contact holes for capacitors wide apart. Therefore, the memory cell area increases and the DRAM is unable to make the most of the characteristic advantage of the open bit line arrangement.
SUMMARY OF THE INVENTION
The present invention has been made in view of those problems in the prior art and it is therefore an object of the present invention to provide a semiconductor integrated circuit device having a small bit line capacitance, excellent in noise resistance, requiring a small cell area and having bit lines arranged in an open bit line arrangement, and to provide a method of fabricating such a semiconductor integrated circuit device.
Typical summaries of the invention is disclosed in this application will be described as follows.
According to a first aspect of the present invention, a semiconductor integrated circuit device having a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells each having a transistor and a capacitor placed on the bit line comprises: active regions formed in a surface of a semiconductor substrate, intersecting adjacent first and second word lines among the plurality of word lines and first bit lines among the plurality of bit lines, extending in a third direction different from the first and the second direction and having a predetermined width along a fourth direction perpendicular to the third direction; first and second semiconductor regions formed in the active regions and serving as sources and drains of the tr
Asano Isamu
Matsuoka Hideyuki
Nagai Ryo
Sekiguchi Tomonori
Takemura Riichiro
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tran Thien F
LandOfFree
Semiconductor integrated circuit device and a method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and a method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and a method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3304324