Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-19
2010-10-19
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C326S037000, C326S041000, C327S147000, C327S295000
Reexamination Certificate
active
07818706
ABSTRACT:
Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O11b, supplied with a clock signal from outside, and a PLL12, connected to the I/O11b, and adapted for routing an internal clock signal, generated on the basis of the clock signal, to DRAM macros14. The PLL12generates the internal clock signal by multiplying the frequency of the clock signal. The internal clock signal generated is distributed via buffer13to each macro cell in need of the internal clock signal. Part of the DRAM macros may be replaced by logic macro cells.
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Japanese Patent Office issued a Japanese Office Action dated Dec. 1, 2008, Application No. 2005-148294.
Do Thuan
NEC Electronics Corporation
Nguyen Nha T
Young & Thompson
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