Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2007-03-22
2009-06-02
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S692000
Reexamination Certificate
active
07541683
ABSTRACT:
A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.
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patent: 7049642 (2006-05-01), Shinjo
patent: 7259467 (2007-08-01), Inagawa
patent: 7323788 (2008-01-01), Miyaki et al.
patent: 2005/0035468 (2005-02-01), Andreini et al.
patent: 2005-93575 (2005-04-01), None
Sakurabayashi Taro
Sonohara Hideo
NEC Electronics Corporation
Potter Roy K
Young & Thompson
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