Semiconductor integrated circuit device

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S233110, C365S233120

Reexamination Certificate

active

07616519

ABSTRACT:
The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

REFERENCES:
patent: 5774410 (1998-06-01), Nakase
patent: 6327212 (2001-12-01), Ishikawa et al.
patent: 6449197 (2002-09-01), Hiraki et al.
patent: 6463529 (2002-10-01), Miller et al.
patent: 6523132 (2003-02-01), Harari et al.
patent: 6788616 (2004-09-01), Takahashi
patent: 2002/0018394 (2002-02-01), Takahashi
patent: 8-212784 (1996-08-01), None
patent: 2005-85344 (2005-03-01), None

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