Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2007-01-16

2008-12-02

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

07460421

ABSTRACT:
There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.

REFERENCES:
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patent: 6804156 (2004-10-01), Ito
patent: 6937533 (2005-08-01), Hojo et al.
patent: 2003/0106001 (2003-06-01), Kurumada et al.
patent: 2004/0066684 (2004-04-01), Ito
patent: 2006/0083085 (2006-04-01), Ikegami
patent: 2006/0161744 (2006-07-01), Fukuda
patent: 2004-133970 (2004-04-01), None
Ouellette et al, Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2002, pp. 191-194.

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