Semiconductor integrated circuit device

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement

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365177, 365 51, G11C 700

Patent

active

052914453

ABSTRACT:
A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

REFERENCES:
patent: 4675849 (1987-06-01), Kinoshita
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4855958 (1989-08-01), Ikeda
patent: 4945513 (1990-07-01), Ueda

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