Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2007-09-11
2007-09-11
Tran, Michael (Department: 2827)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S230030
Reexamination Certificate
active
10988673
ABSTRACT:
A semiconductor integrated circuit device includes a plurality of first memory cells each of which includes a cell transistor whose gate terminal is connected to a word line and a ferroelectric capacitor which is connected at one end to a source terminal of the cell transistor. The drain terminals of the cell transistors of are used as a first local bit line, the other end of each of the ferroelectric capacitors are used as a first plate line. A first reset transistor has a source terminal connected to the first plate line and a drain terminal connected to the first local bit line. A first block selection transistor has a source terminal connected to the first local bit line and a drain terminal connected to a first bit line.
REFERENCES:
patent: 6262910 (2001-07-01), Takata et al.
patent: 6574133 (2003-06-01), Takashima
patent: 6930907 (2005-08-01), Sberno et al.
patent: 6980460 (2005-12-01), Shiratake et al.
patent: 6982447 (2006-01-01), Kim
patent: 2004/0252542 (2004-12-01), Hoya et al.
patent: 7-262768 (1995-10-01), None
patent: 10-255483 (1998-09-01), None
patent: 11-177036 (1999-07-01), None
patent: 2000-22010 (2000-01-01), None
patent: 2000-123578 (2000-04-01), None
patent: 2000-187990 (2000-07-01), None
patent: 2001-283585 (2001-10-01), None
patent: 2003-30977 (2003-01-01), None
Daisaburo Takashima, et al., “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 787-792.
Daisaburo Takashima, “Overview and Trend of Chain FeRAM Architecture”, IEICE Trans. Electron, vol. E84-C, No. 6, Jun. 2001, pp. 747-756.
Shigeo Onishi, et al., “A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure”, IEDM, Dec. 1994, pp. 843-846.
Kabushiki Kaisha Toshiba
Tran Michael
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3785154