Semiconductor integrated circuit device

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S230030

Reexamination Certificate

active

10988673

ABSTRACT:
A semiconductor integrated circuit device includes a plurality of first memory cells each of which includes a cell transistor whose gate terminal is connected to a word line and a ferroelectric capacitor which is connected at one end to a source terminal of the cell transistor. The drain terminals of the cell transistors of are used as a first local bit line, the other end of each of the ferroelectric capacitors are used as a first plate line. A first reset transistor has a source terminal connected to the first plate line and a drain terminal connected to the first local bit line. A first block selection transistor has a source terminal connected to the first local bit line and a drain terminal connected to a first bit line.

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Daisaburo Takashima, et al., “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 787-792.
Daisaburo Takashima, “Overview and Trend of Chain FeRAM Architecture”, IEICE Trans. Electron, vol. E84-C, No. 6, Jun. 2001, pp. 747-756.
Shigeo Onishi, et al., “A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure”, IEDM, Dec. 1994, pp. 843-846.

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