Semiconductor integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S400000

Reexamination Certificate

active

10619039

ABSTRACT:
Interconnections are formed over an interlayer insulating film which covers MISFETQ1formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

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Lee, et al., “An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI)”, 1996, Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159.
Office Action of Korean Application No. 10-1998-0010428 dated Jan. 31, 2005 with English language translation.

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